Active-HDL environment Verilog language floating-point adders timing diagrams УДК 004.021 временные диаграммы среда Active-HDL суммирующие устройства чисел с плавающей запятой UDC 519.688 UDC 004.021 alignment difference arithmetic multi‑row codes carry organization code ordering computation process convolution operation model coverage; efficiency digit slice digital device modeling flowchart hardware cost macro operations method; decision tree; characteristic vector; reduction of the coverage table; assessment of the complexity of the procedure modeling operational element processed bit domain sorting algorithm УДК 519.688 аппаратные затраты