Wild horse optimization algorithm implementation in 7-level packed U-cell multilevel inverter to mitigate total harmonic distortion

• Datum: 2024
• Hauptverfasser: Ebrahimi, F., Windarko, N. A., Gunawan, A. I.
• Format: Artikel
• Sprache: English
• Veröffentlicht: National Technical University "Kharkiv Polytechnic Institute" and Аnatolii Pidhornyi Institute of Power Machines and Systems of NAS of Ukraine 2024
• Schlagworte: packed U-cell multilevel inverter; total harmonic distortion; modified pulse width modulation; wild horse optimization algorithm
• Online Zugang: http://eie.khpi.edu.ua/article/view/298371
• Назва журналу: Electrical Engineering & Electromechanics

Introduction. Multilevel inverters (MLIs) are a popular industrial and, more especially, renewable energy application solution. This is because of its appetite for filters, low distortion class, and capacity to provide a multilayer output voltage that resembles a pure sine waveform. The novelty is in applying the wild horse optimization algorithm (WHOA) to adjust the sinusoidal pulse width modulation (SPWM) technique by producing the optimal reference signal parameters in a new multilevel inverter architecture known as the packed U-cell multilevel inverter (PUC-MLI). Purpose. This study helps with the idea of new inverter architecture and a modified pulse width modulation (MPWM) method to make the multilevel inverter smaller, cheaper, and with less total harmonic distortion (THD). Methods. We use the proposed approach to control a 7-level, single-phase PUC-MLI. The WHOA is used to discover the optimal parameters of the additional reference sine signal after being compared with SPWM to evaluate its performance in harmonic reduction. The simulation’s outcome was validated by building a PUC-MLI prototype. Results. Experimental results and simulations validate the effectiveness of the suggested approach. The WHOA-improved MPWM approach achieves a significant reduction in THD on the PUC-MLI output voltage, as indicated by the results. Practical value. THD in MLI output voltage will be reduced without spending any cost. The suggested solution works with many MLI topologies with varying output voltage levels. References 20, tables 6, figures 12.