Translation of VHDL Sequential Statements
VHDL is one of the most popular languages used in logic synthesis tools. It has variety of statements which make it powerful and flexible tool. But, as the result, it is rather difficult to create a compiler of VHDL language, especially the one which will be used in a logic synthesis. There is littl...
Збережено в:
| Дата: | 2008 |
|---|---|
| Автор: | |
| Формат: | Стаття |
| Мова: | English |
| Опубліковано: |
Інститут проблем моделювання в енергетиці ім. Г.Є. Пухова НАН України
2008
|
| Назва видання: | Электронное моделирование |
| Теми: | |
| Онлайн доступ: | http://dspace.nbuv.gov.ua/handle/123456789/101562 |
| Теги: |
Додати тег
Немає тегів, Будьте першим, хто поставить тег для цього запису!
|
| Назва журналу: | Digital Library of Periodicals of National Academy of Sciences of Ukraine |
| Цитувати: | Translation of VHDL Sequential Statements / M. Radziewicz // Электронное моделирование. — 2008. — Т. 30, № 2. — С. 69-80. — Бібліогр.: 19 назв. — англ. |
Репозитарії
Digital Library of Periodicals of National Academy of Sciences of Ukraine| Резюме: | VHDL is one of the most popular languages used in logic synthesis tools. It has variety of statements which make it powerful and flexible tool. But, as the result, it is rather difficult to create a compiler of VHDL language, especially the one which will be used in a logic synthesis. There is little information about translation algorithms used to generate hardware representation from VHDL sources. The algorithms for few sequential statements of VHDL language are developed. Apart from the algorithms themselves the paper presents a lot of information about translation process itself and all possible problems which may occur during it. Proposed solution was implemented in a compilerwhich uses Boolean equations as an output format. The paper includes results of tests which were performed to check practical usability boundaries of proposed algorithms. |
|---|