APA (7th ed.) Citation

Charyulu, E. R., & Lal Kishore, K. (2009). Integrated Circuit Delay Analysis for 500 Million Transistors: Parameter Optimization using Taguchi Approach. Электронное моделирование.

Chicago Style (17th ed.) Citation

Charyulu, Evln Ranga, and K. Lal Kishore. "Integrated Circuit Delay Analysis for 500 Million Transistors: Parameter Optimization Using Taguchi Approach." Электронное моделирование 2009.

MLA (8th ed.) Citation

Charyulu, Evln Ranga, and K. Lal Kishore. "Integrated Circuit Delay Analysis for 500 Million Transistors: Parameter Optimization Using Taguchi Approach." Электронное моделирование, 2009.

Warning: These citations may not always be 100% accurate.