Integrated Circuit Delay Analysis for 500 Million Transistors: Parameter Optimization using Taguchi Approach

• Published in: Электронное моделирование
• Date: 2009
• Main Authors: Evln Ranga Charyulu, Lal Kishore, K.
• Format: Article
• Language: English
• Published: Інститут проблем моделювання в енергетиці ім. Г.Є. Пухова НАН України 2009
• Subjects: Элементы, узлы и устройства
• Online Access: https://nasplib.isofts.kiev.ua/handle/123456789/101433
• Journal Title: Digital Library of Periodicals of National Academy of Sciences of Ukraine
• Cite this: Integrated Circuit Delay Analysis for 500 Million Transistors: Parameter Optimization using Taguchi Approach / Evln Ranga Charyulu, K. Lal Kishore // Электронное моделирование. — 2009. — Т. 31, № 1. — С. 89-96. — Бібліогр.: 23 назв. — англ.

Delay analysis of 500 million transistor integrated circuit is optimized using test plan L8, in the form of an orthogonal array and a software for automatic design and analysis of experiments both based on the Taguchi approach. Optimal levels of physical parameters and key components, namely, the nu...