Translation of VHDL Sequential Statements

• Published in: Электронное моделирование
• Date: 2008
• Main Author: Radziewicz, M.
• Format: Article
• Language: English
• Published: Інститут проблем моделювання в енергетиці ім. Г.Є. Пухова НАН України 2008
• Subjects: Вычислительные процессы и системы
• Online Access: https://nasplib.isofts.kiev.ua/handle/123456789/101562
• Journal Title: Digital Library of Periodicals of National Academy of Sciences of Ukraine
• Cite this: Translation of VHDL Sequential Statements / M. Radziewicz // Электронное моделирование. — 2008. — Т. 30, № 2. — С. 69-80. — Бібліогр.: 19 назв. — англ.

VHDL is one of the most popular languages used in logic synthesis tools. It has variety of statements which make it powerful and flexible tool. But, as the result, it is rather difficult to create a compiler of VHDL language, especially the one which will be used in a logic synthesis. There is littl...