Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs

• Published in: Semiconductor Physics Quantum Electronics & Optoelectronics
• Date: 2011
• Main Authors: Rana, A.K., Chand, N., Kapoor, V.
• Format: Article
• Language: English
• Published: Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України 2011
• Online Access: https://nasplib.isofts.kiev.ua/handle/123456789/117721
• Journal Title: Digital Library of Periodicals of National Academy of Sciences of Ukraine
• Cite this: Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs / Ashwani K. Rana, Narottam Chand, Vinod Kapoor // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2011. — Т. 14, № 2. — С. 203-208. — Бібліогр.: 15 назв. — англ.

Semiconductor devices with a low gate leakage current are preferred for low
 power application. As the devices are scaled down, sidewall spacer for CMOS transistor
 in nano-domain becomes increasingly critical and plays an important role in device
 performance evaluation. In this work, gate tunneling currents have been modeled for a
 nano-scale MOSFET having different high-k dielectric spacer such as SiO₂, Si₃N₄,
 Al₂O₃, HfO₂. The proposed model is compared and contrasted with Santaurus simulation
 results and reported experimental result to verify the accuracy of the model. The
 agreement found was good, thus validating the developed analytical model. It is observed
 in the results that gate leakage current decreases with the increase of dielectric constant
 of the device spacer. Further, it is also reported that the spacer materials impact the
 threshold voltage, on current, off current, drain induced barrier lowering and subthreshold
 slope of the device.