Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs

Semiconductor devices with a low gate leakage current are preferred for low power application. As the devices are scaled down, sidewall spacer for CMOS transistor in nano-domain becomes increasingly critical and plays an important role in device performance evaluation. In this work, gate tunnelin...

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Опубліковано в: :	Semiconductor Physics Quantum Electronics & Optoelectronics
Дата:	2011
Автори:	Rana, A.K., Chand, N., Kapoor, V.
Формат:	Стаття
Мова:	English
Опубліковано:	Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України 2011
Онлайн доступ:	https://nasplib.isofts.kiev.ua/handle/123456789/117721
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Цитувати:	Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs / Ashwani K. Rana, Narottam Chand, Vinod Kapoor // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2011. — Т. 14, № 2. — С. 203-208. — Бібліогр.: 15 назв. — англ.

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spelling	Rana, A.K. Chand, N. Kapoor, V. 2017-05-26T13:07:37Z 2017-05-26T13:07:37Z 2011 Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs / Ashwani K. Rana, Narottam Chand, Vinod Kapoor // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2011. — Т. 14, № 2. — С. 203-208. — Бібліогр.: 15 назв. — англ. 1560-8034 PACS 85.30.Tv https://nasplib.isofts.kiev.ua/handle/123456789/117721 Semiconductor devices with a low gate leakage current are preferred for low power application. As the devices are scaled down, sidewall spacer for CMOS transistor in nano-domain becomes increasingly critical and plays an important role in device performance evaluation. In this work, gate tunneling currents have been modeled for a nano-scale MOSFET having different high-k dielectric spacer such as SiO₂, Si₃N₄, Al₂O₃, HfO₂. The proposed model is compared and contrasted with Santaurus simulation results and reported experimental result to verify the accuracy of the model. The agreement found was good, thus validating the developed analytical model. It is observed in the results that gate leakage current decreases with the increase of dielectric constant of the device spacer. Further, it is also reported that the spacer materials impact the threshold voltage, on current, off current, drain induced barrier lowering and subthreshold slope of the device. en Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України Semiconductor Physics Quantum Electronics & Optoelectronics Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs Article published earlier
institution	Digital Library of Periodicals of National Academy of Sciences of Ukraine
collection	DSpace DC
title	Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs
spellingShingle	Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs Rana, A.K. Chand, N. Kapoor, V.
title_short	Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs
title_full	Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs
title_fullStr	Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs
title_full_unstemmed	Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs
title_sort	impact of sidewall spacer on gate leakage behavior of nano-scale mosfets
author	Rana, A.K. Chand, N. Kapoor, V.
author_facet	Rana, A.K. Chand, N. Kapoor, V.
publishDate	2011
language	English
container_title	Semiconductor Physics Quantum Electronics & Optoelectronics
publisher	Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України
format	Article
description	Semiconductor devices with a low gate leakage current are preferred for low power application. As the devices are scaled down, sidewall spacer for CMOS transistor in nano-domain becomes increasingly critical and plays an important role in device performance evaluation. In this work, gate tunneling currents have been modeled for a nano-scale MOSFET having different high-k dielectric spacer such as SiO₂, Si₃N₄, Al₂O₃, HfO₂. The proposed model is compared and contrasted with Santaurus simulation results and reported experimental result to verify the accuracy of the model. The agreement found was good, thus validating the developed analytical model. It is observed in the results that gate leakage current decreases with the increase of dielectric constant of the device spacer. Further, it is also reported that the spacer materials impact the threshold voltage, on current, off current, drain induced barrier lowering and subthreshold slope of the device.
issn	1560-8034
url	https://nasplib.isofts.kiev.ua/handle/123456789/117721
citation_txt	Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs / Ashwani K. Rana, Narottam Chand, Vinod Kapoor // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2011. — Т. 14, № 2. — С. 203-208. — Бібліогр.: 15 назв. — англ.
work_keys_str_mv	AT ranaak impactofsidewallspacerongateleakagebehaviorofnanoscalemosfets AT chandn impactofsidewallspacerongateleakagebehaviorofnanoscalemosfets AT kapoorv impactofsidewallspacerongateleakagebehaviorofnanoscalemosfets
first_indexed	2025-11-26T01:42:45Z
last_indexed	2025-11-26T01:42:45Z
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fulltext	Semiconductor Physics, Quantum Electronics & Optoelectronics, 2011. V. 14, N 2. P. 203-208. PACS 85.30.Tv Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs Ashwani K. Rana1, Narottam Chand2, Vinod Kapoor1 1Department of Electronics and Communication, National Institute of Technology, Hamirpur Hamirpur (H.P)-177005, India E-mail: ashwani_paper@yahoo.com; kapoor@nitham.ac.in 2Department of Computer Science and Engineering, National Institute of Technology, Hamirpur Hamirpur(H.P.)-177005, India E-mail: nar@nitham.ac.in Abstract. Semiconductor devices with a low gate leakage current are preferred for low power application. As the devices are scaled down, sidewall spacer for CMOS transistor in nano-domain becomes increasingly critical and plays an important role in device performance evaluation. In this work, gate tunneling currents have been modeled for a nano-scale MOSFET having different high-k dielectric spacer such as SiO2, Si3N4, Al2O3, HfO2. The proposed model is compared and contrasted with Santaurus simulation results and reported experimental result to verify the accuracy of the model. The agreement found was good, thus validating the developed analytical model. It is observed in the results that gate leakage current decreases with the increase of dielectric constant of the device spacer. Further, it is also reported that the spacer materials impact the threshold voltage, on current, off current, drain induced barrier lowering and sub- threshold slope of the device. Keywords: MOSFET, spacer, leakage current. Manuscript received 30.09.10; accepted for publication 16.03.11; published online 30.06.11. 1. Introduction To improve the performances of electronic devices, the size of their active components is scaled down according to the International Technology Roadmap for Semiconductors (ITRS) [1]. As we approach the nano- regime, a whole new set of problems regarding the device performance arises [2]. The control of leakage power is one of the most important issues for scaling MOSFET towards nano-regime [3]. For nano-scale MOSFET, gate leakage current is considered as a dominant leakage component as compared to sub- threshold leakage [4], as gate oxide thickness approaches its manufacturing and physically limiting value of less than 2 nm [2]. Hence, accurate estimation of the gate leakage current is essential to appreciate the total off- state power dissipation. Numerous models have been developed numerically [5-7] in the past for calculating the tunneling current, but this approach is not always practical and is time consuming. Schuegraf et al. [8, 9] have derived a simple analytical formula to represent direct tunneling through a trapezoidal barrier. However, this model suffers from various limitations such as (i) gate current does not approach to zero as gate voltage goes to zero and does not fit experimental data at sub-1-V gate bias range, (ii) the assumption of constant effective mass for all energies is not accurate, (iii) non- consideration of quantum effects. Lee and Hu [10, 11] proposed a semi-empirical model by introducing the correction function to Schuegraf’s analytical model to take care of above-mentioned secondary effect. However, this model has not considered the edge direct tunneling current (EDT). In [12], direct tunneling current expressions have been developed both for channel gate tunneling current and EDT including polydepletion effect and quantization effect with four adjustable parameters. This model does not include: (i) the non- uniform dopant profile in polygate in vertical direction resulted due to low energy ion implantation, (ii) additional depletion layer at the gate edges due to gate length scaling down, and (iii) gate oxide barrier © 2011, V. Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine 203 Semiconductor Physics, Quantum Electronics & Optoelectronics, 2011. V. 14, N 2. P. 203-208. lowering due to image charges across the Si/SiO2 interface. These nano-scale effects (NSE) are inevitable for nano-scale devices operating into deep sub-50-nm regime. Therefore, it is mandatory to include these NSE effects in nano-scale MOSFET to achieve an accurate estimation of the gate tunneling current. In this work, an effective model has been developed for analyzing the gate tunneling current of nano-scale NMOSFET by considering the NSE effect that are difficult to ignore at nano-scale regime. This work mainly focuses on the impact of device spacer on gate leakage current and other device parameters. The rest of the paper is organized as follows. In Section 2, modeling of the gate tunneling current is developed. The device structure and design used for simulation of set up is presented in Section 3. The results obtained are discussed in Section 4. Finally, concluding remarks are offered in Section 5. 2. Theoretical model In ultra short-channel MOSFETs, in addition to gate to channel direct tunneling current, the source/drain extensions (overlap regions) direct tunneling current known as edge direct tunneling current (EDT) has been identified as the principal source of off-state power dissipation in VLSI chips because source/drain extensions (overlap regions) under poly-silicon gate represent a significant fraction of the device, as they do not scale at the same rate as the gate length. Therefore, the evaluation of EDT is critical for state of the art MOSFETs. Modeling of the direct tunneling current analytically has been largely based on the WKB approximation [8]. The discrepancies that were present in the original WKB approximation [8] have been rectified in [10, 11] by introducing few adjusting parameters but they neglected the nano-scale effects. In our work, we adopt this model to evaluate the direct tunneling current from channel and overlap region in the nano-scale regime by taking the nano-scale effect into account. In this scheme, the value of fitting parameter for channel and overlap region has been used as 0.6 and 0.45, respectively, with oxide spacer to match the overall best fit with Santaurus simulation and also with the experimental results reported in [12]. The T ),( ovchα ox refers to the physical oxide thickness and effective mass of the carrier in the oxide has been used as 0.40 mo through this work. The total gate leakage current is given by gdogsogcg IIII ++= , (1) where is the gate-to-channel tunneling current, is the gate-to-source overlap region gate tunneling current, and is the gate-to-drain overlap region tunneling current. Since drain to source V gcI gsoI gdoI ds is taken to be zero for simplification, so Ig can be modified as below gsoovovgcg IIIII 2; =+= . (2) The channel current Igc and EDT current Iov per micrometer can be written as: Igc = Jch × Leff; Iov = Jov × Lov. Leff = Lg – 2Lov, where Lg is the total gate length, Lov is the overlap gate length, and Leff is the effective gate length. The channel current density Jch and overlap current density Jov are modeled as follows: ),(),(),( ovchWKBovchFovch TACJ = , (3) where oxeffb qA επφ= _ 3 8 , is the correction term incorporated in [10, 11] and is the modified WKB transmission probability and are modified for channel and overlap region. is the permittivity of the gate oxide and ),( ovchFC ),( ovchT oxε effb _φ is the effective barrier height, calculated as below, ,_ φΔ−φ=φ beffb (4) . 16 2 44 4 1 32 _ 3 ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ επ φ = πε = πε =φΔ gi effbeff gigi gi gi gi Nq T qVqE (5) φΔ is the reduction in the barrier height at the high-k/Si interface from bφ , so that the barrier height becomes effb _φ . This reduction in barrier height is due to image charges across the interface. This barrier reduction is of great interest, since it modulates the gate tunneling current. , . \|\| 1120 exp ),(_ ),( ),( _ _),( _ ),( _ ovchDTC ox g effb ovchox ovch effb effbovchox effb ovch N T VVV c ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ ⎥ ⎥ ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎢ ⎢ ⎣ ⎡ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ φ − ⎟⎟ ⎟ ⎠ ⎞ ⎜⎜ ⎜ ⎝ ⎛ + φ φ− φ= = α , \|\|3 \|\| 1128 exp ),( 2 3 _ ),(2 3 _ ),( ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎣ ⎡ ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎣ ⎡ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ φ −−φπ− = ovchox effb ovchox effbox ovchWKB Ehq V m T ( ) ( ) ⎪ ⎪ ⎪ ⎪ ⎪ ⎩ ⎪⎪ ⎪ ⎪ ⎪ ⎨ ⎧ > ⎪⎩ ⎪ ⎨ ⎧ ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎣ ⎡ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ − −+ ε < ⎪⎩ ⎪ ⎨ ⎧ ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎣ ⎡ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ − −+ ε = 0for exp1ln 0for exp1ln )( g tinv thg tinv gi ox g tacc FBg tacc gi ox chDTC V vn VV vn t V vn VV vn t N ( ) ( ) ⎪ ⎪ ⎪ ⎪ ⎪ ⎩ ⎪⎪ ⎪ ⎪ ⎪ ⎨ ⎧ > ⎪⎩ ⎪ ⎨ ⎧ ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎣ ⎡ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ −+ ε < ⎪⎩ ⎪ ⎨ ⎧ ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎣ ⎡ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ −+ ε = 0for exp1ln 0for exp1ln )( g tinv ge tinv gi ox g tacc g tacc gi ox ovDTC V vn V vn t V vn V vn t N © 2011, V. Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine 204 Semiconductor Physics, Quantum Electronics & Optoelectronics, 2011. V. 14, N 2. P. 203-208. Where is the fitting parameter depending upon channel or source/drain overlap tunneling, and are the swing parameters, V ),( ovchα invn accn FB represents the flat band voltage, denotes the density of carrier in channel/overlap region depending upon MOSFET biasing condition, and is the effective gate voltage excluding polygate non-uniformity and gate length effect and is equal to , where is the voltage drop due to polydepletion in the polygate. ),( ovchDTCN geV polyg VV − polyV © 2011, V. Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine ovchDTCN , The default values of and are (S is the sub-threshold swing and is the thermal voltage) and 1, respectively. The correction factor and transmission probability are different for channel and source/drain overlap region, because both channel and overlap components have different values of and . It is because of the fact that overlap region has almost zero flat band voltage, as both SDE region and overlying polygate Si are heavily doped n invn accn tvS / tv ( )ovchFC , ( )ovchWKBT , ( )ovchoxV , ),( ovchDTCN + regions. has been given differently for both region as in (12) and (13). The gate oxide voltage for the channel and SDE overlap are calculated as follows. ( ) oxV Case (i): when Vg > 0. In this biasing condition for MOSFET device, there is a depletion layer in the polygate thereby causing an additional potential drop across the gate. The SDE region enters into accumulation and substrate region enters into the week inversion below Vth and strong inversion beyond Vth. Therefore, both the channel and EDT component are present and are comparable. Case (ii): when VFB < Vg < 0. Here, gate tunneling current is dominated by the EDT where electric field is such that electron are directed from the accumulated polygate into the overlap region. On the other hand, substrate is in depletion/weak inversion and constitutes a negligible tunneling current. This region of biasing is primarily responsible for off- state power dissipation. Thus, EDT plays an important role in the evaluation of off-state power dissipation. Case (iii): when Vg < VFB. In this region of operation, substrate goes into accumulation. As a result, both current components become comparable. The voltage across the gate oxide for different region of operation is as follows: ( ) ( )⎩ ⎨ ⎧ >−φ− <−φ− = 0for 0for gFBsge gFBsg ox VVV VVV V (6) Where is the surface band bending of the substrate and are calculated for channel and overlap region depending upon the biasing condition of the MOSFET device including the poly-non-uniformity, gate length effects and image force barrier lowering. sφ The gate effective voltage in the gate is derived as follows: ( ) .1 )(2 1 )( 2 2 2 2 21 ⎥ ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎢ ⎣ ⎡ − ε φ−−ε + ε ε +Δ−Δ−φ+=∴ oxpolysi soFBgox ox oxpolysi ppsoFBge TNq VVTNq VVVV (7) This equation includes the non-uniformity in the gate dopant profile through the term and fringing field effect, i.e. gate length effect through a term 1pVΔ 2pVΔ . soφ is surface band bending of the substrate by taking the quantization effect into account. The potential drop 1pVΔ due to non-uniform dopant profile in poly-Si gate, caused by low energy implantation, is calculated as below ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ =Δ − − bottompoly toppoly p N N q kTV ln1 .(8) toppolyN − and are the doping concentration at the top and bottom of the poly-silicon gate. The potential drop bottompolyN − 2pVΔ due to the gate length effect, caused by very short gate lengths, is given below: ( ) ,cm V2 2 dg d d p CL qAN C Q V = Δ ≈Δ (9) , 1 cos3 ln ⎥ ⎥ ⎥ ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎢ ⎢ ⎢ ⎣ ⎡ ⎪⎭ ⎪ ⎬ ⎫ ⎪⎩ ⎪ ⎨ ⎧ ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ − π+ ⎪⎭ ⎪ ⎬ ⎫ ⎪⎩ ⎪ ⎨ ⎧ ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ − π− π ε δ= F giF F giF spacer d T TT T TT C (10) where A denotes the triangular area of the additional charge, Lg is the gate length, Cd is the depletion capacitance in the sidewalls [13], εgi is the permittivity of the device spacer, TF is the thickness of the device spacer, Tgi is the thickness of the gate insulator, and δ is the fitting parameter normally equal to 0.95. 3. Simulation set up Fig. 1 shows the device structure used for simulation in Santaurus simulator. The deep S/D region is composed of a heavily doped silicon and a silicide contact. Doping the silicon S/D region is assumed to be very high, 1×1020 cm–3, which is close to the solid solubility limit and introduces negligible silicon resistance. The dimension of the silicon S/D region is taken as 50 nm long and 20 nm high. This gives a large contact area resulting in a small contact resistance. The heavily doped silicon called deep S/D region extends into the silicon film at both ends and constitutes the extended S/D for the device (labelled by ‘‘S1’’and ‘‘D1’’ in Fig. 1). The doping concentration of the acceptors in the silicon channel region is assumed to be graded due to diffusion of dopant ions from heavily doped S/D region with a peak value of 1×1018 cm–3 and 205 Semiconductor Physics, Quantum Electronics & Optoelectronics, 2011. V. 14, N 2. P. 203-208. Fig. 1. NMOSFET device structure used in simulation. 1×1017 cm–3near the channel. The doping concentration in the poly-silicon gate is 1×1022 cm–3 at the top and 1×1020 cm–3 at the bottom of poly-silicon gate, i.e. interface of oxide and silicon. The halo implantation made around S/D also reduces short-channel effects, such as the punch-through current, drain induced barrier lowering (DIBL), and threshold voltage roll-off for different non-overlap lengths. The MOSFET has a 50-nm-thick n+ poly-Si gate with the metallurgical gate length of 25 nm and a 1-nm gate oxide. The MOSFET with Lmet of 25 nm was designed to have a VT of 0.23 V with SiO2 as spacer. We determined VT by using a linear extrapolation of the linear portion of the GSDS VI − curve at low drain voltages. The operating voltage for the devices is 1 V. The simulation study has been conducted in two dimensions, hence all the results are in the units of per unit channel width. The simulation of the device is performed by using Santaurus design suite [14, 15] with drift-diffusion, density gradient quantum correction and advanced physical model being turned on. 4. Results and discussion In this section, computation of gate tunneling currents for a n-channel nano-scale MOSFET having different sidewall spacer such as SiO2 (k = 3.9), Si3N4 (k = 7.5), Al2O3 (k = 9.0) and HfO2 (k = 22) have been carried out. This model is computationally efficient and easy-to- realize. This model calculates the gate tunneling current by using α(ch/ov) as fitting parameters. Thus, this model is applicable to many alternate high-k nano-MOSFET simply by adjusting the fitting parameter. Variation of the total gate tunneling current with a gate bias for a given values of gate insulator thickness has been presented for possible alternative sidewall spacer such as SiO2, Si3N4, Al2O3 and HfO2. The impact of sidewall spacer on the device threshold voltage, off current, on current, DIBL and sub-threshold slope (SS) is also reported in results. 0.0 0.2 0.4 0.6 0.8 1.0 1E-9 1E-8 1E-7 1E-6 G at e Tu nn el in g C ur re nt (A /u m ) Gate Bias (V) Santaurus Simulation Our Model with NSE Model without NSE Fig 2. Comparison of model with simulated data for gate oxide thickness of Tox = 1.0 nm with oxide spacer, metallurgical gate length of Lmet = 25 nm and S/D overlap length of Lov = 10 nm in nano-scale regime. The comparison between the simulated data and the model value for the gate tunneling current is presented in Fig. 2 for the value Lmet = 25 nm, Lov = 10 nm, Tox = 1.0 nm. The model value while considering the nano-scale effect shows good agreement with the simulated value over the entire positive gate bias range, certifying the high accuracy of the proposed analytical modelling. Model also shows good agreement with simulated data for various sidewall spacers but with different values of the fitting parameter as listed in Table 1. It is also shown that the model value without any nano-scale effect does not show good agreement with the simulated value, emphasizing the need to include nano-scale effect. Similarly, the model is also verified in Fig. 3 with experimental data published in [12] for value Lg = 0.17 µm, Lov = 10 nm, Tox = 1.85 nm and Wg = 10 µm. The substrate doping and poly-silicon gate doping have been taken to be and , respectively. The model value also shows good agreement with the experimental data over the entire gate bias range, certifying the high accuracy of the proposed analytical modelling. 317 cm101.4 −× 320 cm105 −× Fig. 4 shows the variation of the gate tunneling current and off current of the NMOS device with S/D overlap length for optimization of the latter at a given gate bias of 0.6 V and gate oxide thickness of 1.0 nm. It is observed that off current for a device under consideration is slightly less at S/D overlap length of 5 nm. Therefore, S/D overlap length of 5.0 nm is considered in further results. Table 1. Fitting parameter for calculation of the gate tunneling current through different sidewall spacers. Parameter SiO2 Si3N4 Al2O3 HfO2 chα 0.6 0.62 0.71 0.78 ovα 0.45 0.49 0.53 0.55 © 2011, V. Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine 206 Semiconductor Physics, Quantum Electronics & Optoelectronics, 2011. V. 14, N 2. P. 203-208. -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 G at e Tu nn el in g C ur re nt (A /u m ) Gate Bias (V) Experimental Data Model Data Fig. 3. Comparison of the model with experimental data for Nsub = 4.1×1017 cm–3 and Npoly = 5×1019 cm–3 with oxide spacer. © 2011, V. Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine Fig. 4. Gate tunneling current and off current vs S/D overlap length for Tox = 1.0 nm, Lmet = 25 nm. Fig. 5 shows variation of the gate tunneling current with the gate bias for various sidewall spacers at gate oxide thickness of 1.0 nm. It is observed that gate leakage current improves with the introduction of sidewall spacer of increasing dielectric constant K. The application of high-k spacer enhances the fringing electric field thereby reducing the effective gate voltage. This reduction lowers the transverse electric field responsible for carrier tunneling through gate oxide. Consequently, the gate leakage current reduces as dielectric constant of the sidewall spacer increases. In Fig. 6, variation of the device threshold voltage with sidewall spacer is presented. As the dielectric constant of the sidewall spacer increases, the fringing field increases. These field lines finally induce an electric field from the source-to-channel thereby reducing the source-to-channel barrier height. Since the threshold voltage of the device is controlled by the injection of electrons over this potential barrier, it decreases with increasing dielectric constant of the sidewall spacer. Thus, sidewall spacers with a larger dielectric permittivity reduce the threshold voltage owing to the enhanced value of fringing electric field. 0.0 0.2 0.4 0.6 0.8 1.0 1E-9 1E-8 1E-7 Tox=1.0 nm G at e Tu nn el in g Cu rre nt (A /u m ) SiO 2 Spacer Si3N4 Spacer Al 2 O 3 Spacer HfO2 Spacer Fig. 5. Gate tunneling current vs gate bias for different sidewall spacer in nano-scale regime at Lmet = 25 nm and Lov = 5.0 nm. 2 3 4 5 6 7 8 9 10 0.0000000 0.0000002 0.0000004 0.0000006 0.0000008 x Tox=1.0 nm C ur re nt (A /u m ) S/D Overlap Length (nm) Gate Tunneling Current (A/um) Off Current (A/um) SiO2 Si3N4 Al2O3 HfO2 0.15 0.16 0.17 0.18 0.19 0.20 0.21 0.22 0.23 0.24 Th re sh ol d Vo lta ge ( V) MOSFET Spacer with increasing Dielectric Constant(K) Fig. 6. Device threshold voltage vs sidewall spacer with Lmet = 25 nm and Lov = 5.0 nm. SiO2 Si3N4 Al2O3 HfO2 60 65 70 75 80 Drain Induced Barrier Lowering(DIBL) Subthreshold Slope(SS) MOSFET Spacers with increasing K D IB L (m V /V ) 80 85 90 95 SS (m V )/dec) Fig. 7. Drain induced barrier lowering (DIBL) and sub- threshold slope (SS) vs sidewall spacer with Lmet = 25 nm and Lov = 5.0 nm. Fig. 7 shows that DIBL increases with increase in dielectric constant of the sidewall spacer. It is due to the fact that the increased effect of fringing field on channel by the application of high-k sidewall spacer weakens the gate control over the channel region of a MOSFET. Due to this decrease in gate control, the drain electrode is tightly coupled to the channel, and the lateral electric 207 Semiconductor Physics, Quantum Electronics & Optoelectronics, 2011. V. 14, N 2. P. 203-208. © 2011, V. Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine SiO 2 Si3N 4 Al2O 3 H fO 2 1E-6 1E-5 1E-4 1E-3 0.01 0.1 C ur re nt (A /u m ) M O SFET Spacers w ith increasing K O n C urren t (Ion) O ff C urren t (Ioff) Fig. 8. On and off currents vs sidewall spacer with Lmet = 25 nm and Lov = 5.0 nm. field from the drain reaches a larger distance into the channel. Consequently, this electrically closer proximity of drain to source gives rise to higher drain-induced barrier lowering in MOS transistors. It is also shown in Fig. 7 that sub-threshold characteristics degrade due to decrease in the threshold voltage. As shown in Fig. 8, on current (Ion) and off current (Ioff) degrade slightly due to a decrease in the threshold voltage as well as due to the degraded sub-threshold characteristics. 5. Conclusion The impact of sidewall spacer on gate leakage current and other device parameters is studied using the gate tunnel model and extensive device simulations. A high-k sidewall spacer lowers the gate leakage current while increases the sub-threshold slope with drain induced barrier lowering. Sidewall spacers with a larger dielectric permittivity reduce the threshold voltage owing to the enhanced value of fringing electric field. It is found that the use of high-k sidewall spacers also degrades the on and off current marginally. References 1. Online. Available: http://www.itrs.net/reports.html 2. C.H. Choi, K.Y. Nam, Z. Yu, and R.W. Dutton, Impact of gate direct tunneling current on circuit performance: A simulation study // IEEE Trans. Electron Devices, 48, p. 2823-2829 (Dec. 2001). 3. F. Rana, S. Tiwari, and D. Buchanan, Self- consistent modeling of accumulation layers and tunneling currents through very thin oxides // Appl. Phys. Lett., 69, p. 1104-1106 (1996). 4. S.-H. Lo, D.A. Buchanan, Y. Taur, and W. Wang, Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra- thin-oxide nMOSFETs // IEEE Electron Device Lett., 18, p. 209-211 (May 1997). 5. W.K. Shih et al., Modeling gate leakage current in nMOS structures due to tunneling through an ultra- thin oxide // Solid State Electron., 42, p. 997-1006 (June 1998). 6. K. Roy, S. Mukhopadhyay, and H. Mahmoodi- Meimand, Leakage current mechanisms and leakage reduction techniques in deep- submicrometer CMOS circuits // Proc. IEEE, 91(2), p. 305-327 (Feb. 2003). 7. Y. Ando and T. Itoh, Calculation of transmission tunneling current across arbitrary potential barriers // J. Appl. Phys., 61(4), p. 1497 (1987). 8. K.F. Schuegraf, C.C. King, and C. Hu, Ultra-thin silicon dioxide leakage current and scaling limit // Symposium on VLSI Technology Digest of Technical Papers, p. 18-19 (1992). 9. K.F. Schuegraf and C. Hu, Hole injection SiO2 breakdown model for very low voltage lifetime extrapolation // IEEE Trans. on Electron Devices, 41(5), 1994. 10. W.C. Lee and C. Hu, Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling // Symposium on VLSI Technology Digest of Technical Papers, p. 198 (2000). 11. W.C. Lee and C. Hu, Modeling CMOS tunneling currents through ultrathin gate oxide due to conduc- tion- and valence-band electron and hole tunneling // IEEE Trans. Electron Devices, 48(7), (2001). 12. Xin (Ben) Gu, Ten-Lon Chen, Gennady Gildenblat,, Glenn O. Workman, Surya Veeraraghavan, Shye Shapira, and Kevin Stiles, A surface potential-based compact model of n- MOSFET gate-tunneling current // IEEE Trans. Electron Devices, 51(1), (2004). 13. Steve Shao-Shiun Chung and Tung-Chi Li // IEEE Trans. Electron Devices, 39(3), (1992). 14. ISE TCAD: Synopsys Santaurus Device User Manual, 1995-2005, Synopsys, Mountain View, CA. 15. ISE TCAD: Synopsys Santaurus Device simulator. 208 http://www.itrs.net/reports.html

Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs

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