Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs
Semiconductor devices with a low gate leakage current are preferred for low
 power application. As the devices are scaled down, sidewall spacer for CMOS transistor
 in nano-domain becomes increasingly critical and plays an important role in device
 performance evaluation. In...
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| Published in: | Semiconductor Physics Quantum Electronics & Optoelectronics |
|---|---|
| Date: | 2011 |
| Main Authors: | , , |
| Format: | Article |
| Language: | English |
| Published: |
Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України
2011
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| Online Access: | https://nasplib.isofts.kiev.ua/handle/123456789/117721 |
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| Journal Title: | Digital Library of Periodicals of National Academy of Sciences of Ukraine |
| Cite this: | Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs / Ashwani K. Rana, Narottam Chand, Vinod Kapoor // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2011. — Т. 14, № 2. — С. 203-208. — Бібліогр.: 15 назв. — англ. |
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Digital Library of Periodicals of National Academy of Sciences of Ukraine| _version_ | 1862569401772933120 |
|---|---|
| author | Rana, A.K. Chand, N. Kapoor, V. |
| author_facet | Rana, A.K. Chand, N. Kapoor, V. |
| citation_txt | Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs / Ashwani K. Rana, Narottam Chand, Vinod Kapoor // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2011. — Т. 14, № 2. — С. 203-208. — Бібліогр.: 15 назв. — англ. |
| collection | DSpace DC |
| container_title | Semiconductor Physics Quantum Electronics & Optoelectronics |
| description | Semiconductor devices with a low gate leakage current are preferred for low
power application. As the devices are scaled down, sidewall spacer for CMOS transistor
in nano-domain becomes increasingly critical and plays an important role in device
performance evaluation. In this work, gate tunneling currents have been modeled for a
nano-scale MOSFET having different high-k dielectric spacer such as SiO₂, Si₃N₄,
Al₂O₃, HfO₂. The proposed model is compared and contrasted with Santaurus simulation
results and reported experimental result to verify the accuracy of the model. The
agreement found was good, thus validating the developed analytical model. It is observed
in the results that gate leakage current decreases with the increase of dielectric constant
of the device spacer. Further, it is also reported that the spacer materials impact the
threshold voltage, on current, off current, drain induced barrier lowering and subthreshold
slope of the device.
|
| first_indexed | 2025-11-26T01:42:45Z |
| format | Article |
| fulltext | |
| id | nasplib_isofts_kiev_ua-123456789-117721 |
| institution | Digital Library of Periodicals of National Academy of Sciences of Ukraine |
| issn | 1560-8034 |
| language | English |
| last_indexed | 2025-11-26T01:42:45Z |
| publishDate | 2011 |
| publisher | Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України |
| record_format | dspace |
| spelling | Rana, A.K. Chand, N. Kapoor, V. 2017-05-26T13:07:37Z 2017-05-26T13:07:37Z 2011 Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs / Ashwani K. Rana, Narottam Chand, Vinod Kapoor // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2011. — Т. 14, № 2. — С. 203-208. — Бібліогр.: 15 назв. — англ. 1560-8034 PACS 85.30.Tv https://nasplib.isofts.kiev.ua/handle/123456789/117721 Semiconductor devices with a low gate leakage current are preferred for low
 power application. As the devices are scaled down, sidewall spacer for CMOS transistor
 in nano-domain becomes increasingly critical and plays an important role in device
 performance evaluation. In this work, gate tunneling currents have been modeled for a
 nano-scale MOSFET having different high-k dielectric spacer such as SiO₂, Si₃N₄,
 Al₂O₃, HfO₂. The proposed model is compared and contrasted with Santaurus simulation
 results and reported experimental result to verify the accuracy of the model. The
 agreement found was good, thus validating the developed analytical model. It is observed
 in the results that gate leakage current decreases with the increase of dielectric constant
 of the device spacer. Further, it is also reported that the spacer materials impact the
 threshold voltage, on current, off current, drain induced barrier lowering and subthreshold
 slope of the device. en Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України Semiconductor Physics Quantum Electronics & Optoelectronics Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs Article published earlier |
| spellingShingle | Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs Rana, A.K. Chand, N. Kapoor, V. |
| title | Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs |
| title_full | Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs |
| title_fullStr | Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs |
| title_full_unstemmed | Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs |
| title_short | Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs |
| title_sort | impact of sidewall spacer on gate leakage behavior of nano-scale mosfets |
| url | https://nasplib.isofts.kiev.ua/handle/123456789/117721 |
| work_keys_str_mv | AT ranaak impactofsidewallspacerongateleakagebehaviorofnanoscalemosfets AT chandn impactofsidewallspacerongateleakagebehaviorofnanoscalemosfets AT kapoorv impactofsidewallspacerongateleakagebehaviorofnanoscalemosfets |