Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs

• Datum: 2011
• Hauptverfasser: Rana, A.K., Chand, N., Kapoor, V.
• Format: Artikel
• Sprache: English
• Veröffentlicht: Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України 2011
• Schriftenreihe: Semiconductor Physics Quantum Electronics & Optoelectronics
• Online Zugang: https://nasplib.isofts.kiev.ua/handle/123456789/117721
• Назва журналу: Digital Library of Periodicals of National Academy of Sciences of Ukraine
• Zitieren: Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs / Ashwani K. Rana, Narottam Chand, Vinod Kapoor // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2011. — Т. 14, № 2. — С. 203-208. — Бібліогр.: 15 назв. — англ.

Semiconductor devices with a low gate leakage current are preferred for low power application. As the devices are scaled down, sidewall spacer for CMOS transistor in nano-domain becomes increasingly critical and plays an important role in device performance evaluation. In this work, gate tunnelin...