Error detection and debugging on information in communication system using single electron circuit based binary decision diagram

In digital information error happens in a communication system due to path delay or processing error/delay and can be detected by logical circuit which has been implemented here by binary decision diagrams with single electron movement from root node to leaf node. Binary decision diagrams are the re...

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Опубліковано в: :Semiconductor Physics Quantum Electronics & Optoelectronics
Дата:2003
Автори: Biswas, A.K., Sarkar, S.K.
Формат: Стаття
Мова:English
Опубліковано: Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України 2003
Онлайн доступ:https://nasplib.isofts.kiev.ua/handle/123456789/118049
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Назва журналу:Digital Library of Periodicals of National Academy of Sciences of Ukraine
Цитувати:Error detection and debugging on information in communication system using single electron circuit based binary decision diagram / A.K. Biswas, S.K. Sarkar // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2003. — Т. 6, № 3. — С. 357-364. — Бібліогр.: 13 назв. — англ.

Репозитарії

Digital Library of Periodicals of National Academy of Sciences of Ukraine
id nasplib_isofts_kiev_ua-123456789-118049
record_format dspace
spelling Biswas, A.K.
Sarkar, S.K.
2017-05-28T14:30:04Z
2017-05-28T14:30:04Z
2003
Error detection and debugging on information in communication system using single electron circuit based binary decision diagram / A.K. Biswas, S.K. Sarkar // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2003. — Т. 6, № 3. — С. 357-364. — Бібліогр.: 13 назв. — англ.
1560-8034
https://nasplib.isofts.kiev.ua/handle/123456789/118049
In digital information error happens in a communication system due to path delay or processing error/delay and can be detected by logical circuit which has been implemented here by binary decision diagrams with single electron movement from root node to leaf node. Binary decision diagrams are the representations of logic functions factored recursively with respect to input variables. Errors in the received information can be detected by the error detection circuit consisting of binary decision diagram circuits. In this technique a maximum errors of four bits can be detected in a received information of 32 bit length. However, by rearranging the received bit patterns it is possible to detect the error(s) in any bit of the received information. Every message signal is transmitted with a tag value. After detecting the error and removing the tag bit(s), the receiver finds out the corrected information.
S. K. Sarkar thankfully acknowledges the financial support obtained from University Grants Commission vide order no. F. 14-32 2000 dated 12th October 2000.
en
Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України
Semiconductor Physics Quantum Electronics & Optoelectronics
Error detection and debugging on information in communication system using single electron circuit based binary decision diagram
Article
published earlier
institution Digital Library of Periodicals of National Academy of Sciences of Ukraine
collection DSpace DC
title Error detection and debugging on information in communication system using single electron circuit based binary decision diagram
spellingShingle Error detection and debugging on information in communication system using single electron circuit based binary decision diagram
Biswas, A.K.
Sarkar, S.K.
title_short Error detection and debugging on information in communication system using single electron circuit based binary decision diagram
title_full Error detection and debugging on information in communication system using single electron circuit based binary decision diagram
title_fullStr Error detection and debugging on information in communication system using single electron circuit based binary decision diagram
title_full_unstemmed Error detection and debugging on information in communication system using single electron circuit based binary decision diagram
title_sort error detection and debugging on information in communication system using single electron circuit based binary decision diagram
author Biswas, A.K.
Sarkar, S.K.
author_facet Biswas, A.K.
Sarkar, S.K.
publishDate 2003
language English
container_title Semiconductor Physics Quantum Electronics & Optoelectronics
publisher Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України
format Article
description In digital information error happens in a communication system due to path delay or processing error/delay and can be detected by logical circuit which has been implemented here by binary decision diagrams with single electron movement from root node to leaf node. Binary decision diagrams are the representations of logic functions factored recursively with respect to input variables. Errors in the received information can be detected by the error detection circuit consisting of binary decision diagram circuits. In this technique a maximum errors of four bits can be detected in a received information of 32 bit length. However, by rearranging the received bit patterns it is possible to detect the error(s) in any bit of the received information. Every message signal is transmitted with a tag value. After detecting the error and removing the tag bit(s), the receiver finds out the corrected information.
issn 1560-8034
url https://nasplib.isofts.kiev.ua/handle/123456789/118049
citation_txt Error detection and debugging on information in communication system using single electron circuit based binary decision diagram / A.K. Biswas, S.K. Sarkar // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2003. — Т. 6, № 3. — С. 357-364. — Бібліогр.: 13 назв. — англ.
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first_indexed 2025-12-07T19:39:28Z
last_indexed 2025-12-07T19:39:28Z
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