Superconductor digital electronics: scalability and energy efficiency issues (Review Article)

Superconductor digital electronics using Josephson junctions as ultrafast switches and magnetic-flux encoding of information was proposed over 30 years ago as a sub-terahertz clock frequency alternative to semiconductor electronics based on complementary metal-oxide-semiconductor (CMOS) transistors....

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Datum:2016
1. Verfasser: Tolpygo, S.K.
Format: Artikel
Sprache:English
Veröffentlicht: Фізико-технічний інститут низьких температур ім. Б.І. Вєркіна НАН України 2016
Schriftenreihe:Физика низких температур
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Online Zugang:https://nasplib.isofts.kiev.ua/handle/123456789/129109
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Назва журналу:Digital Library of Periodicals of National Academy of Sciences of Ukraine
Zitieren:Superconductor digital electronics: scalability and energy efficiency issues (Review Article) / Sergey K. Tolpygo // Физика низких температур. — 2016. — Т. 42, № 5. — С. 463-485. — Бібліогр.: 153 назв. — англ.

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Digital Library of Periodicals of National Academy of Sciences of Ukraine
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Zusammenfassung:Superconductor digital electronics using Josephson junctions as ultrafast switches and magnetic-flux encoding of information was proposed over 30 years ago as a sub-terahertz clock frequency alternative to semiconductor electronics based on complementary metal-oxide-semiconductor (CMOS) transistors. Recently, interest in developing superconductor electronics has been renewed due to a search for energy saving solutions in applications related to high-performance computing. The current state of superconductor electronics and fabrication processes are reviewed in order to evaluate whether this electronics is scalable to a very large scale integration (VLSI) required to achieve computation complexities comparable to CMOS processors. A fully planarized process at MIT Lincoln Laboratory, perhaps the most advanced process developed so far for superconductor electronics, is used as an example. The process has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm, and a thin superconducting layer for making compact high-kinetic-inductance bias inductors. All circuit layers are fully planarized using chemical mechanical planarization (CMP) of SiO₂ interlayer dielectric. The physical limitations imposed on the circuit density by Josephson junctions, circuit inductors, shunt and bias resistors, etc., are discussed. Energy dissipation in superconducting circuits is also reviewed in order to estimate whether this technology, which requires cryogenic refrigeration, can be energy efficient. Fabrication process development required for increasing the density of superconductor digital circuits by a factor of ten and achieving densities above 10⁷ Josephson junctions per cm² is described.