Superconductor digital electronics: scalability and energy efficiency issues (Review Article)

Superconductor digital electronics using Josephson junctions as ultrafast switches and magnetic-flux encoding of information was proposed over 30 years ago as a sub-terahertz clock frequency alternative to semiconductor electronics based on complementary metal-oxide-semiconductor (CMOS) transistors....

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Опубліковано в: :Физика низких температур
Дата:2016
Автор: Tolpygo, S.K.
Формат: Стаття
Мова:Англійська
Опубліковано: Фізико-технічний інститут низьких температур ім. Б.І. Вєркіна НАН України 2016
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Онлайн доступ:https://nasplib.isofts.kiev.ua/handle/123456789/129109
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Назва журналу:Digital Library of Periodicals of National Academy of Sciences of Ukraine
Цитувати:Superconductor digital electronics: scalability and energy efficiency issues (Review Article) / Sergey K. Tolpygo // Физика низких температур. — 2016. — Т. 42, № 5. — С. 463-485. — Бібліогр.: 153 назв. — англ.

Репозитарії

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author Tolpygo, S.K.
author_facet Tolpygo, S.K.
citation_txt Superconductor digital electronics: scalability and energy efficiency issues (Review Article) / Sergey K. Tolpygo // Физика низких температур. — 2016. — Т. 42, № 5. — С. 463-485. — Бібліогр.: 153 назв. — англ.
collection DSpace DC
container_title Физика низких температур
description Superconductor digital electronics using Josephson junctions as ultrafast switches and magnetic-flux encoding of information was proposed over 30 years ago as a sub-terahertz clock frequency alternative to semiconductor electronics based on complementary metal-oxide-semiconductor (CMOS) transistors. Recently, interest in developing superconductor electronics has been renewed due to a search for energy saving solutions in applications related to high-performance computing. The current state of superconductor electronics and fabrication processes are reviewed in order to evaluate whether this electronics is scalable to a very large scale integration (VLSI) required to achieve computation complexities comparable to CMOS processors. A fully planarized process at MIT Lincoln Laboratory, perhaps the most advanced process developed so far for superconductor electronics, is used as an example. The process has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm, and a thin superconducting layer for making compact high-kinetic-inductance bias inductors. All circuit layers are fully planarized using chemical mechanical planarization (CMP) of SiO₂ interlayer dielectric. The physical limitations imposed on the circuit density by Josephson junctions, circuit inductors, shunt and bias resistors, etc., are discussed. Energy dissipation in superconducting circuits is also reviewed in order to estimate whether this technology, which requires cryogenic refrigeration, can be energy efficient. Fabrication process development required for increasing the density of superconductor digital circuits by a factor of ten and achieving densities above 10⁷ Josephson junctions per cm² is described.
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spelling Tolpygo, S.K.
2018-01-16T13:33:06Z
2018-01-16T13:33:06Z
2016
Superconductor digital electronics: scalability and energy efficiency issues (Review Article) / Sergey K. Tolpygo // Физика низких температур. — 2016. — Т. 42, № 5. — С. 463-485. — Бібліогр.: 153 назв. — англ.
0132-6414
PACS: 85.25.–j, 85.25.Am, 85.25.Cp, 85.25.Hv
https://nasplib.isofts.kiev.ua/handle/123456789/129109
Superconductor digital electronics using Josephson junctions as ultrafast switches and magnetic-flux encoding of information was proposed over 30 years ago as a sub-terahertz clock frequency alternative to semiconductor electronics based on complementary metal-oxide-semiconductor (CMOS) transistors. Recently, interest in developing superconductor electronics has been renewed due to a search for energy saving solutions in applications related to high-performance computing. The current state of superconductor electronics and fabrication processes are reviewed in order to evaluate whether this electronics is scalable to a very large scale integration (VLSI) required to achieve computation complexities comparable to CMOS processors. A fully planarized process at MIT Lincoln Laboratory, perhaps the most advanced process developed so far for superconductor electronics, is used as an example. The process has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm, and a thin superconducting layer for making compact high-kinetic-inductance bias inductors. All circuit layers are fully planarized using chemical mechanical planarization (CMP) of SiO₂ interlayer dielectric. The physical limitations imposed on the circuit density by Josephson junctions, circuit inductors, shunt and bias resistors, etc., are discussed. Energy dissipation in superconducting circuits is also reviewed in order to estimate whether this technology, which requires cryogenic refrigeration, can be energy efficient. Fabrication process development required for increasing the density of superconductor digital circuits by a factor of ten and achieving densities above 10⁷ Josephson junctions per cm² is described.
I am very grateful to all my colleagues at MIT Lincoln
 Laboratory who are involved with fabrication process development
 for superconductor electronics, especially to
 Vladimir Bolkhovsky and Scott Zarr, to Terry Weir and
 Alex Wynn for their part in device testing, and to Mark
 Gouker and Leonard Johnson for the discussions and management
 of the program. I would like to thank Vasili K.
 Semenov, Alex F. Kirichenko, Timur Filippov, Quentin
 Herr, Marc Manheimer, and D. Scott Holmes for useful
 discussions. My special thanks are to Daniel E. Oates for
 reading the manuscript and suggesting numerous improvements.
 This research is based upon work supported by the Office
 of the Director of National Intelligence (ODNI), Intelligence
 Advanced Research Projects Activity (IARPA), via
 Air Force Contract FA872105C0002. The views and conclusions
 contained herein are those of the author and
 should not be interpreted as necessarily representing the
 official policies or endorsements, either expressed or implied,
 of the ODNI, IARPA, or the U.S. Government. The
 U.S. Government is authorized to reproduce and distribute
 reprints for Governmental purposes notwithstanding any
 copyright annotation thereon.
en
Фізико-технічний інститут низьких температур ім. Б.І. Вєркіна НАН України
Физика низких температур
К 100-летию со дня рождения К.Б. Толпыго
Superconductor digital electronics: scalability and energy efficiency issues (Review Article)
Article
published earlier
spellingShingle Superconductor digital electronics: scalability and energy efficiency issues (Review Article)
Tolpygo, S.K.
К 100-летию со дня рождения К.Б. Толпыго
title Superconductor digital electronics: scalability and energy efficiency issues (Review Article)
title_full Superconductor digital electronics: scalability and energy efficiency issues (Review Article)
title_fullStr Superconductor digital electronics: scalability and energy efficiency issues (Review Article)
title_full_unstemmed Superconductor digital electronics: scalability and energy efficiency issues (Review Article)
title_short Superconductor digital electronics: scalability and energy efficiency issues (Review Article)
title_sort superconductor digital electronics: scalability and energy efficiency issues (review article)
topic К 100-летию со дня рождения К.Б. Толпыго
topic_facet К 100-летию со дня рождения К.Б. Толпыго
url https://nasplib.isofts.kiev.ua/handle/123456789/129109
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