Integral Nonlinearity of Second-Order Single-Bit Sigma-Delta Modulator
The simulation model of single-bit second-order sigma-delta modulator and analog-to-digital converter (ADC) based on this modulator is developed. The study of influence of all components parameters on integral nonlinearity of ADC is carried out by the model. As revealed, there are no influence of se...
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| Zitieren: | Integral Nonlinearity of Second-Order Single-Bit Sigma-Delta Modulator / Haimeng Sun, R. Kochan, O. Kochan, Jun Su // Технічна електродинаміка. — 2016. — № 6. — С. 63-68. — Бібліогр.: 16 назв. — англ. |
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Sun, Haimeng Kochan, R. Kochan, O. Su, Jun 2018-09-19T14:30:07Z 2018-09-19T14:30:07Z 2016 Integral Nonlinearity of Second-Order Single-Bit Sigma-Delta Modulator / Haimeng Sun, R. Kochan, O. Kochan, Jun Su // Технічна електродинаміка. — 2016. — № 6. — С. 63-68. — Бібліогр.: 16 назв. — англ. 1607-7970 https://nasplib.isofts.kiev.ua/handle/123456789/141976 621.317.7 The simulation model of single-bit second-order sigma-delta modulator and analog-to-digital converter (ADC) based on this modulator is developed. The study of influence of all components parameters on integral nonlinearity of ADC is carried out by the model. As revealed, there are no influence of second integrator nonlinearity on ADC nonlinearity. Разработана имитационная модель однобитного сигма-дельта модулятора второго порядка и аналого-цифрового преобразователя (АЦП) на его базе. С использованием этой модели проведено исследование влияния параметров компонентов на интегральную нелинейность АЦП. Выявлено отсутствие влияния нелинейности второго интегратора на нелинейность АЦП. Розроблено імітаційну модель однобітного сигма-дельта модулятора другого порядку та аналого-цифрового перетворювача на його базі. З використанням цієї моделі проведено дослідження впливу параметрів компонентів на інтегральну нелінійність АЦП. Виявлено відсутність впливу нелінійності другого інтегратора на нелінійність АЦП. en Інститут електродинаміки НАН України Технічна електродинаміка Інформаційно-вимірювальні системи в електроенергетиці Integral Nonlinearity of Second-Order Single-Bit Sigma-Delta Modulator Интегральная нелинейность однобитного сигма-дельта модулятора второго порядка Інтегральна нелінійність однобітного сигма-дельта модулятора другого порядку Article published earlier |
| institution |
Digital Library of Periodicals of National Academy of Sciences of Ukraine |
| collection |
DSpace DC |
| title |
Integral Nonlinearity of Second-Order Single-Bit Sigma-Delta Modulator |
| spellingShingle |
Integral Nonlinearity of Second-Order Single-Bit Sigma-Delta Modulator Sun, Haimeng Kochan, R. Kochan, O. Su, Jun Інформаційно-вимірювальні системи в електроенергетиці |
| title_short |
Integral Nonlinearity of Second-Order Single-Bit Sigma-Delta Modulator |
| title_full |
Integral Nonlinearity of Second-Order Single-Bit Sigma-Delta Modulator |
| title_fullStr |
Integral Nonlinearity of Second-Order Single-Bit Sigma-Delta Modulator |
| title_full_unstemmed |
Integral Nonlinearity of Second-Order Single-Bit Sigma-Delta Modulator |
| title_sort |
integral nonlinearity of second-order single-bit sigma-delta modulator |
| author |
Sun, Haimeng Kochan, R. Kochan, O. Su, Jun |
| author_facet |
Sun, Haimeng Kochan, R. Kochan, O. Su, Jun |
| topic |
Інформаційно-вимірювальні системи в електроенергетиці |
| topic_facet |
Інформаційно-вимірювальні системи в електроенергетиці |
| publishDate |
2016 |
| language |
English |
| container_title |
Технічна електродинаміка |
| publisher |
Інститут електродинаміки НАН України |
| format |
Article |
| title_alt |
Интегральная нелинейность однобитного сигма-дельта модулятора второго порядка Інтегральна нелінійність однобітного сигма-дельта модулятора другого порядку |
| description |
The simulation model of single-bit second-order sigma-delta modulator and analog-to-digital converter (ADC) based on this modulator is developed. The study of influence of all components parameters on integral nonlinearity of ADC is carried out by the model. As revealed, there are no influence of second integrator nonlinearity on ADC nonlinearity.
Разработана имитационная модель однобитного сигма-дельта модулятора второго порядка и аналого-цифрового преобразователя (АЦП) на его базе. С использованием этой модели проведено исследование влияния параметров компонентов на интегральную нелинейность АЦП. Выявлено отсутствие влияния нелинейности второго интегратора на нелинейность АЦП.
Розроблено імітаційну модель однобітного сигма-дельта модулятора другого порядку та аналого-цифрового перетворювача на його базі. З використанням цієї моделі проведено дослідження впливу параметрів компонентів на інтегральну нелінійність АЦП. Виявлено відсутність впливу нелінійності другого інтегратора на нелінійність АЦП.
|
| issn |
1607-7970 |
| url |
https://nasplib.isofts.kiev.ua/handle/123456789/141976 |
| citation_txt |
Integral Nonlinearity of Second-Order Single-Bit Sigma-Delta Modulator / Haimeng Sun, R. Kochan, O. Kochan, Jun Su // Технічна електродинаміка. — 2016. — № 6. — С. 63-68. — Бібліогр.: 16 назв. — англ. |
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2025-11-26T19:14:30Z |
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2025-11-26T19:14:30Z |
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| fulltext |
ISSN 1607-7970. Техн. електродинаміка. 2016. № 6 63
ІНФОРМАЦІЙНО-ВИМІРЮВАЛЬНІ СИСТЕМИ В ЕЛЕКТРОЕНЕРГЕТИЦІ
УДК 621.317.7
INTEGRAL NONLINEARITY OF SECOND-ORDER SINGLE-BIT SIGMA-DELTA MODULATOR
Sun Haimeng1, R. Kochan2, O. Kochan2, Su Jun3
1 − Jimei University Chengyi College, 185 Yinjiang Road, 361021, XiaMen, China,
2 − Lviv Polytechnic National University,
12 Bandera str., Lviv, 79013, Ukraine. E-mail: kochan.roman@gmail.com
3 − Hubei University of Technology, Wuhan, 430068, China.
The simulation model of single-bit second-order sigma-delta modulator and analog-to-digital converter (ADC) based
on this modulator is developed. The study of influence of all components parameters on integral nonlinearity of ADC is
carried out by the model. As revealed, there are no influence of second integrator nonlinearity on ADC nonlinearity.
References 16, figures 9, table 1.
Key words: sigma-Delta Modulator, Integral Nonlinearity, Error Correction.
Introduction. Wide implementation of processors and digital signal processing algorithms in data acquisition
and measurement systems brings to that analog-to-digital converters (ADC) became the necessary component of such
systems. The metrology characteristics of systems of electrical quantities measurement are mainly defined by metrology
characteristics of used ADCs. Therefore, improvement of metrology characteristics of ADCs is an actual task and it can
give improvement of the accuracy of measurement results.
The segment of precision ADC is filled by the converters based on sigma-delta modulators (SDM). Such ADCs
are in the line of leading companies and are very popular on the market [1, 2]. Their high accuracy is based on
implementation of accuracy improvement methods – null setting and calibration using reference voltage source. These
methods provide correction of additive and multiplicative components of ADC’s error. The residual error of such ADC is
mainly defined by nonlinearity of ADC’s conversion function (CF). Its level is significant and potentially we can
decrease it. For example, 24-bit ADC of AD7714 type has integral nonlinearity not more than 15 ppm [3], and it
corresponds only to 16-th bit. At the same time its effective resolution is up to 22 bit. So the nonlinearity of CF is 6 low
signed “effective” bits or 8 least significant bits - LSB (taking into consideration noise level). Decreasing of ADC’s
nonlinearity provides smoothing of ADC’s CF and can provide design accurate model of measured object [4, 5] or
process [6, 7]. Therefore it is actual to investigate the form of ADC’s nonlinearity.
The complexity of ADC’s nonlinearity correction is associated with its dualistic character: nonlinearity is
systematic for each ADC and random for the set of single type ADC. Besides the parameters of nonlinearity
approximation function depend of the operation mode of ADC. Therefore, the single determination of this function, for
example, after manufacturing, and further correction do not provide significant accuracy improvement of conversion
results.
The set of methods is developed. They provide precision identification of ADC’s CF in the set of testing points
[8]. The number of generated testing points is beginning from one up to some dozen per range depending on the
complexity of the circuit and processing algorithm. However the implementation of these methods for correction of
nonlinear error of ADC demands forming of interpolation curve for whole range. The interpolation function selection
demands investigation of its character. The nonlinearity of sigma-delta ADC’s CF is defined by nonlinearity of forward
signal channel [9, 10] and the purposeful selecting of interpolation function for nonlinearity correction demands study of
the influence of integrator nonlinearity on nonlinearity of SDM and ADC based on SDM. So, the objective of the
presented work is to investigate the character of ADC’s CF nonlinearity for adequate forming of interpolation curve.
Development of simulation model. The exclusively experimental investigation of dependence of SDM’s
nonlinearity on integrators’ nonlinearity could not be informative enough because of:
• influence of the error of reference equipment;
• complexity of precision owing to integrator nonlinearity.
Therefore it is proposed to make investigation by simulation. The results obtained in [10, 11] suppose the
synchronous variation of the parameters of all integrators. This is only one and not typical case for high order SDM
because each integrator is separate component with own parameters and essential divergence between their time
constants [11]. Therefore it necessary to investigate the sensitivity of SDM’s nonlinearity for the cases of independent
integrators and their nonsynchronous combinations.
The structure of single-bit second-order SDM is presented in fig.1. It consists of forward signal and backward signal
channels. The first of them consists of two adders – , two integrators – ∫ and synchronous comparator – SC (which
consists of asynchronous comparator and synchronous D-triger – TT). Backward signal channel consists of single-bit
© Sun Haimeng, Kochan R., Kochan O., Su Jun, 2016
64 ISSN 1607-7970. Техн. електродинаміка. 2016. № 6
digital-to-analog converter – DAC, which is controlled by output code of SDM. Synchronization pulses for TT are
generated by pulse generator – G.
∫∫
Fig. 1
The testing points of SDM (S1, S2, I1, I2, G, C, D) are marked in fig. 1. The dependences of voltage at these testing points
on current are expressed by component equation of simulation model. The system of equations second-order SDM is
( ) ( ) ( )
( ) ( )
( ) ( ) ( )
( ) ( )
( )
( )
( )
( )
( )
( ) ( )( )
( )
( ) ( )( ) ( )( )
( )
( )
( )
( )
1
1 1
1 0
2 1
2 1
2 0
2
2
,
1 ,
,
1 ,
1, 0
,
0, 0
1, , 0,5 ,
0, 0,5 , 1 ,
, 1 0 ,
,
, 1,
, 0,
S X D
t
I S
S I D
t
I S
I
C
I
G
C G G
X
X
X
D
X
U t U t U t
U t U t dt
U t U t U t
U t U t dt
U t
U t
U t
t k T k T
U t
t k T k T
U t U t U t t
N t
N t t
E N t
U t
E N t
τ
τ
⎧ = −
⎪
=
= −
=
⎧ >⎪= ⎨
⎨ ≤⎪⎩
⎧ ∈ ⎡ × + × ⎤⎪ ⎣ ⎦= ⎨
∈ + × + ×⎪⎩
⎧ = ∧ − Δ =⎪= ⎨
− Δ⎪⎩
⎧ =⎪= ⎨
− =⎪⎩
∫
∫
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪⎩
(1)
where XU is the input voltage; XN is the output pulse sequence, which corresponds to input voltage XU ;
1 2 1 2, , , , , ,S S I I C G DU U U U U U U are the voltages of appropriate testing points of SDM; 1 2,τ τ are the time constants of
appropriate integrator; T is the period of pulse generator; k is the integer value; 0→Δt is the time step of simulation;
E is the output voltage of DAC.
Taking into consideration (1) and the discreteness of output signal of SDM for the analog-to-digital conversion n is
computed as ( )∑
+
=
×=
Ml
li
X TiNn (2)
where 2KM = is the maximum number of counts of ADC, which is defined by its resolution K ; 1t is the time of
integrator “entry” into operating mode (after transient process of periodic waveform shaping);
T
tl 1
= is the number of
output signals during time 1t , which are nonregistered because of nonfinishing of transient process.
The input voltage of ADC is computed by expression
2 0,5X
nU E
M
⎛ ⎞′ = × −⎜ ⎟
⎝ ⎠
. (3)
The difference between input voltages defined by (1) and computed in (3) forms error, which is taken into
consideration during analysis
X XU U ′Δ = − . (4)
The main parameters, which cause the integrator nonlinearity, are the limited frequency band and limited gain of
amplifier. The significant effect of these parameters is provided by rather high operating frequency of integrators, which
corresponds to operating frequency of pulse generator. This frequency, for example, for ADC of AD7714 type, is 1 or 2,5
MHz. Some works [9, 11] show the negligible influence of amplifiers limited frequency band on SDM nonlinearity.
Therefore it is rational, first of all, to investigate the influence of amplifiers limited gain on ADCs nonlinearity.
ISSN 1607-7970. Техн. електродинаміка. 2016. № 6 65
This influence we can simulate by linear variation of integrator’s time constant in equation (1) depending on input
signal. It gives the parabolic approximation of integrator CF after integration.
( )
/
/
0 /
1, 0
1 ; ; 1,2,
1, 0
I i
i i i I i
I i
U
s k U s i
Uττ τ
⎧− >⎪= × + × × = =⎨
+ <⎪⎩
(5)
where 0iτ is the “initial” value of time constant of i -th integrator; s is the multiplier, which provides symmetric
variation of time constant for positive and negative input signals; ikτ is the value for variation of time constant of i -th
integrator; /
I iU is the output signal of i -th integrator at previous simulation step.
The developed simulation model is oriented on analysis in time domain and realizes the approach of asynchronous
incrementing modeling with constant time step.
According to [12] the range of SDM and ADC based
on SDM is defined by output voltage of backward DAC,
frequency of pulse generator and time constants of
integrators. The parameters of several SDMs are
computed. These parameters are presented in table. The
variants of ADCs are given in the line with XMAXU . All SDMs in this table provide frequency of pulse generator of 100
kHz, DAC voltage is ± 5 V.
Verification of simulation model. The verification of the developed simulation model is implemented by analysis of
the ADC parameter based on linear model of SDM (1) and model of SDM with taking into account the integrator
nonlinearity. The CF of ADC based on linear model of SDM is step function, approximated by segments of the line,
which covers the origin of coordinates. The approximation error does not exceed the sensitivity of ADC. The integral
nonlinearity of this model is equal to zero over all the range. The oscillograms of signals at all testing points for all SDMs
from table for input voltages of 0 and XMAXU correspond to appropriate signals given in [13-15]. Some of these
oscillograms is presented in fig. 2. The maximum value of all integrator output signal does not exceed voltage of DAC. It
means that SDM operates correctly and in linear mode. Therefore we can consider adequate linear simulation model of
SDM with parameters from table.
The influence of integrator nonlinearity on output signal is described by (5). It gives distortion of all SDM’s signals in
comparison with linear model. Therefore it is impossible to see the influence of nonlinearity by subtraction the signals in
appropriate time. The example of SDM’s signals with nonlinear integrators is presented in fig. 3. These signals are for the
identical conditions and time to the signals presented in fig. 2. As seen, these signals are significant different.
The nonlinearity of the first integrator can be seen by plotting imagining straight line through two extremums at the
ends of segments of polyline, which indicates this integrator output signal.
The plot of the first integrator nonlinearity is presented in fig 4. This line is the segment of parabola and it
corresponds to data in [16]. Therefore the simulation of integrator nonlinearity, at least for the first integrator, is adequate
and correct.
The analogical detection of the second integrator nonlinearity is impossible because of nonlinear character of output
signal with unknown parameters even for linear model of SDM. Therefore, the influence of integrator nonlinearity on
statistical parameters of SDM output signal is analyzed as following. SDM output signals with all linear integrators and
one nonlinear integrator are compared. The distortion level of SDM with nonlinear first integrator for SDMs from table
depending on input voltage is presented in fig. 5. The nonlinearity of the first integrator is equal to 0,1 %. Generally the
nonlinearity of 0,1 % of the first integrator gives 5…50 % distortion of SDM output signal.
The distortion level of SDM with nonlinear second integrator for the same SDMs is presented in fig. 6. In this case,
all curves are random but total distortion level is less than in the case of nonlinear first integrator. Generally the
nonlinearity 0,1 % of the second integrator gives 1,6…45 % distortion of SDM output signal.
The distortion level caused by nonlinearity of the second integrator is 1,1 … 3 times less than distortion level caused
by nonlinearity of the first one. We explain this by longer way of distorted signal of the first integrator in comparison
with the second one. The trend of all curves presented in fig. 6 is declined. We explain this by decreasing the frequency
of integrator output signals in the case of increasing input voltage. It gives the longer sequence of stable comparator
output signal and decreasing of total number of comparator switchings. Therefore the delay of comparator output signal
has less influence on conversion result. The random character of curves we can explain by close loop of SDM structure
and the great step of input voltage simulation. The presented results of developed simulation model confirm its
simplicity, adequacy and informativity. Therefore, we can use this model to study the properties of second-order SDM.
Investigation of Integrator Nonlinearity influence on SDM Nonlinearity. The analysis of integrator nonlinearity
influence and integral nonlinearity of ADC based on SDM is realized by computation of the absolute error of conversion
results using (4). The investigation is carried out for all SDMs presented in table. The level of simulated integrator
nonlinearity is 0,01…10 %. The dependence of ADC integral nonlinearity for different SDMs is presented in fig 7. These
curves are obtained for first integrator nonlinearity of 0,1 %. The proportional curves are obtained for other levels of this
integrator nonlinearity. The dependence of maximum nonlinearity of SDM on first integrator nonlinearity levels is
presented in fig. 8.
XMAXU 2,5 3 3,5 4 4,5
1
1
τ
4103.3 ×
4104.2 ×
4107.1 ×
4101.1 ×
3102.5 ×
2
1
τ
4105 ×
66 ISSN 1607-7970. Техн. електродинаміка. 2016. № 6
-4,0
-3,0
-2,0
-1,0
0,0
1,0
2,0
3,0
10
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15
Time, S
Vo
lta
ge
, V
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Time, S
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Time, S
Vo
lta
ge
, V
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11
10
,0
00
12
10
,0
00
13
10
,0
00
14
10
,0
00
14
Time, S
Vo
lta
ge
, V
0 В; 4 ВX XMAXU U= = 4 ВX XMAXU U= =
Fig. 2
-2,0
-1,0
0,0
1,0
2,0
3,0
4,0
5,0
10
,0
00
00
10
,0
00
01
10
,0
00
02
10
,0
00
02
10
,0
00
03
10
,0
00
04
10
,0
00
05
10
,0
00
06
10
,0
00
06
10
,0
00
07
10
,0
00
08
10
,0
00
09
10
,0
00
10
10
,0
00
10
10
,0
00
11
10
,0
00
12
10
,0
00
13
10
,0
00
14
10
,0
00
14
Time, S
Vo
lta
ge
, V
0,00
0,05
0,10
0,15
0,20
0,25
1,19 1,31 1,43 1,56 1,68 1,80 1,93 2,05 2,18 2,30 2,42
1-st integrator's voltage, V
N
on
lin
ea
rit
y,
m
V
Fig. 3 2,5 В; 2,5 ВX XMAXU U= = Fig. 4
0
10
20
30
40
50
60
0 0,5 1 1,5 2 2,5 3 3,5 4 4,5
Voltage, V
D
is
to
rti
on
le
ve
l,
%
4,5
4
3,5
3
2,5
0
5
10
15
20
25
30
35
40
45
50
0 0,5 1 1,5 2 2,5 3 3,5 4 4,5
Voltage, V
D
is
to
rt
io
n
le
ve
l,%
4,5
4
3,5
3
2,5
Fig. 5
Fig. 6
-50
0
50
100
150
200
250
300
350
400
0,0 0,4 0,7 1,1 1,4 1,8 2,1 2,5 2,8 3,2 3,5 3,9 4,2
Input voltage, V
N
on
lin
ea
rit
y,
u
V
.
1,E-05
1,E-04
1,E-03
1,E-02
1,E-01
1,E+00
0,01 0,03 0,10 0,30 1,00 3,00 10,00
Integrator's nonlinearity, %
N
on
lin
ea
rit
y,
V
Uxmax=4,5 V
Uxmax=4,0 V
Uxmax=3,5 V
Uxmax=3,0 V
Uxmax=2,5 V
Fig. 7 Fig. 8
ISSN 1607-7970. Техн. електродинаміка. 2016. № 6 67
Taking into consideration curves presented in fig. 8 we can compute the nonlinearity rejection factor using the
expression 1
100%
UI NL
NL
K
δΔ
=
Δ
,
where 1UIΔ is the peak-to-peak of first integrator output signal, NLδ is the relative nonlinearity of integrator, NLΔ is the
nonlinearity of SDM.
The plots of nonlinearity rejection factor for nonlinear first integrator are presented in fig. 9. As shown, this factor is
approximately constant for nonlinearity more than 0,03 %. The value of the rejection factor is equal to 8…10 and SDMs
with less range provide less values of rejection factor. The nonlinearity level less than 0,03 % corresponds to removable
value of rejection factor. It could be explained by resolution of SDM model.
0
2
4
6
8
10
12
14
16
0,01 0,03 0,10 0,30 1,00 3,00 10,00
Integrator's nonlinearity, %
R
ej
ec
tio
n
Uxmax=4,5 V Uxmax=4,0 V Uxmax=3,5 V
Uxmax=3,0 V Uxmax=2,5 V
Fig. 9
The methodology of investigation of the second integrator nonlinearity influence on SDM nonlinearity is identical to
the first integrator. Generally five SDMs presented in table I with seven nonlinearity levels from 0,01 to 10 % are studed.
The input voltage step is 0,05 V. The SDM nonlinearity for all cases does not exceed the sensitivity of ADC based on
appropriate SDM. Therefore the nonlinearity rejection factor of second integrator nonlinearity is more than 5000 (ratio of
maximum nonlinearity of integrator to sensitivity of SDM). So the influence of second integrator nonlinearity on SDM
nonlinearity is negligible small in comparison with the influence of the first integrator’s nonlinearity.
Conclusion. The developed simulation model of single-bit second-order SDM provides independent
simulation of all integrators by nonlinear submodels. This model is used to investigate the influence of each integrator
nonlinearity on integral nonlinearity of ADC based on this SDM. The results give a possibility to conclude the
following:
• the first integrator nonlinearity has a complex character of influence on ADC integral nonlinearity;
• the level of nonlinearity of the second integrator at least 500 times less than the influence on ADC
nonlinearity in comparison with influence of first integrator nonlinearity;
• the maximal value of ADC integral nonlinearity is proportional to nonlinearity level of the first integrator;
• the rejection factor of first integrator nonlinearity by ADC based on single-bit second-order SDM is from 8
to 10.
ACKNOWLEDGMENT. THE Authors acknowledge the Ministry of Education and Science of Ukraine for support
by Project No 0115U000446.
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УДК 621.317.7
ИНТЕГРАЛЬНАЯ НЕЛИНЕЙНОСТЬ ОДНОБИТНОГО СИГМА-ДЕЛЬТА МОДУЛЯТОРА ВТОРОГО
ПОРЯДКА
Сун Хайменг1, Р. Кочан2, О. Кочан2, Су Джун3
1 − Колледж Ченгуй Университета Жимей, ул. Юинжианг 185, Ксиамен, 361021, Китай,
2 − Национальный университет «Львовская политехника»,
ул. С. Бандеры, 12, Львов, 79013, Украина, E-mail: kochan.roman@gmail.com
3 − Хубейский технический университет, Вухань, 430068, Китай.
Разработана имитационная модель однобитного сигма-дельта модулятора второго порядка и аналого-циф-
рового преобразователя (АЦП) на его базе. С использованием этой модели проведено исследование влияния
параметров компонентов на интегральную нелинейность АЦП. Выявлено отсутствие влияния нелинейности
второго интегратора на нелинейность АЦП. Библ. 16, рис. 9, табл. 1.
Ключевые слова: сигма-дельта модулятор, интегральная нелинейность, коррекция погрешности.
УДК 621.317.7
ІНТЕГРАЛЬНА НЕЛІНІЙНІСТЬ ОДНОБІТНОГО СИГМА-ДЕЛЬТА МОДУЛЯТОРА ДРУГОГО
ПОРЯДКУ
Сун Хаіменг1, Р.Кочан2, О.Кочан2, Су Джун3
1 − Коледж Ченгуй Університету Жімей, вул. Юінжиганг, 185, Ксіамен, 361021, Китай,
2 − Національний університет «Львівська політехніка»,
вул. С. Бандери, 12, Львів, 79013, Україна, E-mail: kochan.roman@gmail.com
3 − Хубейський технічний університет, Вухань, 430068, Китай.
Розроблено імітаційну модель однобітного сигма-дельта модулятора другого порядку та аналого-цифрового
перетворювача на його базі. З використанням цієї моделі проведено дослідження впливу параметрів ком-
понентів на інтегральну нелінійність АЦП. Виявлено відсутність впливу нелінійності другого інтегратора на
нелінійність АЦП. Бібл. 16, рис. 9, табл. 1.
Ключові слова: сигма-дельта модулятор, інтегральна нелінійність, корекція похибки.
Надійшла 05.02.2016
Остаточний варіант 15.09.2016
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