Модель сумматора с параллельным выполнением микроопераций

• Date: 2005
• Main Authors: Paulin, O. N., Shapo, F. S., Sinegub, N. I.
• Format: Article
• Language: Ukrainian
• Published: PE "Politekhperiodika", Book and Journal Publishers 2005
• Subjects: суммирующие устройства чисел с плавающей запятой; временные диаграммы; моделирование; среда Active-HDL; язык Verilog
• Online Access: https://www.tkea.com.ua/index.php/journal/article/view/TKEA2005.2.17
• Journal Title: Technology and design in electronic equipment

The functioning processes of different types of adders are analyzed through their modeling in Verilog within the Active-HDL environment. Timing diagrams were obtained, confirming the increased performance of adders with parallel execution of micro-operations compared to devices with sequential execu...