Контролепригодная схема двоичного сумматора на основе 16-разрядной группы секций
A testable functional‑logical circuit of a binary adder based on a 16‑bit group of 4‑bit sections is considered. The design provides simultaneous carry propagation within each section and section group, and sequential carry propagation between groups. The circuit was developed within the concept of...
Збережено в:
| Дата: | 2003 |
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| Автор: | |
| Формат: | Стаття |
| Мова: | Українська |
| Опубліковано: |
PE "Politekhperiodika", Book and Journal Publishers
2003
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| Теми: | |
| Онлайн доступ: | https://www.tkea.com.ua/index.php/journal/article/view/TKEA2003.1.21 |
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| Назва журналу: | Technology and design in electronic equipment |
| Завантажити файл: |  |
Репозитарії
Technology and design in electronic equipment| Резюме: | A testable functional‑logical circuit of a binary adder based on a 16‑bit group of 4‑bit sections is considered. The design provides simultaneous carry propagation within each section and section group, and sequential carry propagation between groups. The circuit was developed within the concept of “constant” testability of digital circuits. The proposed scheme features a verifying test of length 11 with respect to all its single constant faults. |
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