Контролепригодная схема двоичного сумматора на основе 16-разрядной группы секций
A testable functional‑logical circuit of a binary adder based on a 16‑bit group of 4‑bit sections is considered. The design provides simultaneous carry propagation within each section and section group, and sequential carry propagation between groups. The circuit was developed within the concept of...
Gespeichert in:
| Datum: | 2003 |
|---|---|
| 1. Verfasser: | |
| Format: | Artikel |
| Sprache: | Ukrainisch |
| Veröffentlicht: |
PE "Politekhperiodika", Book and Journal Publishers
2003
|
| Schlagworte: | |
| Online Zugang: | https://www.tkea.com.ua/index.php/journal/article/view/TKEA2003.1.21 |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| Назва журналу: | Technology and design in electronic equipment |
| Завантажити файл: |  |
Institution
Technology and design in electronic equipment| Zusammenfassung: | A testable functional‑logical circuit of a binary adder based on a 16‑bit group of 4‑bit sections is considered. The design provides simultaneous carry propagation within each section and section group, and sequential carry propagation between groups. The circuit was developed within the concept of “constant” testability of digital circuits. The proposed scheme features a verifying test of length 11 with respect to all its single constant faults. |
|---|