Контролепригодные двухканальные логические схемы цифровых компараторов
Testable dual-channel logic circuits of digital comparators intended for implementation in the form of printed circuit assemblies are considered. The testable logic circuits under consideration possess the property of self-checking with respect to single and unidirectional multiple stuck-at faults i...
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| Veröffentlicht in: | Технологія та конструювання в електронній апаратурі |
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| Datum: | 2002 |
| Heft: | 4–5 |
| Сторінки: | 11-12 |
| ISSN: | 3083-6549 |
| Автори та афіліації: |
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| 1. Verfasser: | |
| Format: | Artikel |
| Sprache: | yo |
| Veröffentlicht: |
PE "Politekhperiodika", Book and Journal Publishers
2002
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| Schlagworte: | |
| Online Zugang: | https://www.tkea.com.ua/index.php/journal/article/view/TKEA2002.4-5.11 |
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| Назва журналу: | Technology and design in electronic equipment |
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Technology and design in electronic equipment| Zusammenfassung: | Testable dual-channel logic circuits of digital comparators intended for implementation in the form of printed circuit assemblies are considered. The testable logic circuits under consideration possess the property of self-checking with respect to single and unidirectional multiple stuck-at faults in the interconnections of their printed circuit assemblies.
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| ISSN: | 3083-6549 |