Умножитель/делитель с повышенным быстродействием - Sinegub, N. I. (PE "Politekhperiodika", Book and Journal Publishers, 2009)
An original structure of a multiplier/divider has been developed, in which at the first stage the hardware combines the operations of multiplication and subtraction of integers in two’s complement code, which increases the device’s performance. Moreover, in the proposed multiplier/divider device, there are no operations of transferring numbers, which also enhances its performance.