Buchumschlag

Проектирование сумматоров в среде Active-HDL с предварительным анализом характеристик

A series of original floating-point adders has been designed. The results of analyzing their operation, based on functional models written in Verilog HDL and simulated in the Active-HDL environment, confirm that preliminary determination of l least significant bits of the exponent difference (align...

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Bibliographische Detailangaben
Datum:2007
Hauptverfasser: Paulin, O. N., Shapo, F. S., Sinegub, N. I., Poleschuk, S. O.
Format: Artikel
Sprache:Ukrainisch
Veröffentlicht: PE "Politekhperiodika", Book and Journal Publishers 2007
Schlagworte:
язык VERILOG
среда Active-HDL
моделирование цифровых устройств
суммирующие устройства чисел с плавающей запятой
выравнивающая разность
временные диаграммы
аппаратные затраты
Online Zugang:https://www.tkea.com.ua/index.php/journal/article/view/TKEA2007.3.09
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Назва журналу:Technology and design in electronic equipment

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Technology and design in electronic equipment
Beschreibung
Zusammenfassung:A series of original floating-point adders has been designed. The results of analyzing their operation, based on functional models written in Verilog HDL and simulated in the Active-HDL environment, confirm that preliminary determination of l least significant bits of the exponent difference (alignment difference) reduces hardware cost while decreasing performance as l increases.

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