Constructing Compact Tests for Functional Verification of VHDL Descriptions of the Finite State Machines
Saved in:
| Date: | 2017 |
|---|---|
| Main Authors: | P. N. Bibilo, V. I. Romanov |
| Format: | Article |
| Language: | English |
| Published: |
2017
|
| Series: | Control Systems and Computers |
| Online Access: | http://jnas.nbuv.gov.ua/article/UJRN-0000746821 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Journal Title: | Library portal of National Academy of Sciences of Ukraine | LibNAS |
Institution
Library portal of National Academy of Sciences of Ukraine | LibNASSimilar Items
-
Constructive description of monogenic functions in finite dimensional commutative algebras
by: V. S. Shpakivskyi
Published: (2015) -
Translation of VHDL Sequential Statements
by: Radziewicz, M.
Published: (2008) -
Insertion semantics of VHDL as electronic design languge
by: O. O. Letychevskyi, et al.
Published: (2022) -
Трансляция VHDL программы в BDD структуры
by: Закутайло, Д.А.
Published: (2003) -
Upper bounds for imbalance of discrete functions realized by sequences of finite-state machines
by: A. N. Aleksejchuk, et al.
Published: (2019)