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Method of parallelization of loops for grid calculation problems on GPU accelerators

The formal parallelizing transformation of a nest of calculation loop for SIMD architecture devices, particularly for graphics processing units applying CUDA technology and heterogeneous clusters is developed. Procedure of transition from sequential to parallel algorithm is described and illustrated...

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Bibliographic Details
Date:	2018
Main Authors:	Doroshenko, А.Yu., Beketov, O.G.
Format:	Article
Language:	Ukrainian
Published:	PROBLEMS IN PROGRAMMING 2018
Subjects:	automatic parallelization loop optimization general-purpose computing on graphics processing units UDC 681.3
Online Access:	https://pp.isofts.kiev.ua/index.php/ojs1/article/view/222
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Journal Title:	Problems in programming
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