Method of parallelization of loops for grid calculation problems on GPU accelerators

• Опубліковано в: PROBLEMS IN PROGRAMMING
• Дата: 2018
• Випуск: 1
• Сторінки: 59-66
• ISSN: 1727-4907
• Автори та афіліації: А.Yu. Doroshenko — Institute of Software Systems NAS of Ukraine; O.G. Beketov — Institute of Software Systems NAS of Ukraine
• Автори: Doroshenko, А.Yu., Beketov, O.G.
• Формат: Стаття
• Мова: Українська
• Опубліковано: PROBLEMS IN PROGRAMMING 2018
• Теми: automatic parallelization; loop optimization; general-purpose computing on graphics processing units; UDC 681.3
• Онлайн доступ: https://pp.isofts.kiev.ua/index.php/ojs1/article/view/222
• Назва журналу: Problems in programming

The formal parallelizing transformation of a nest of calculation loop for SIMD architecture devices, particularly for graphics processing units applying CUDA technology and heterogeneous clusters is developed. Procedure of transition from sequential to parallel algorithm is described and illustrated...