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Low-power architecture for CIL-code hardware processor
In the article the authors present the architecture of a hardware CIL processor, which is capable to execute CIL instructions as native code. The CIL hardware engine is implemented on the top of the low-power DSP architecture, and the CIL processor has two execution cores: DSP and CIL. Such solution...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Інститут програмних систем НАН України
2005
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| Subjects: | |
| Online Access: | http://dspace.nbuv.gov.ua/handle/123456789/1372 |
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