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Low-power architecture for CIL-code hardware processor

Low-power architecture for CIL-code hardware processor

In the article the authors present the architecture of a hardware CIL processor, which is capable to execute CIL instructions as native code. The CIL hardware engine is implemented on the top of the low-power DSP architecture, and the CIL processor has two execution cores: DSP and CIL. Such solution...

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Bibliographic Details
Main Authors: Chapyzhenka, A., Ragozin, D., Umnov, A.
Format: Article
Language:English
Published: Інститут програмних систем НАН України 2005
Subjects:
Інструментальні засоби і середовища програмування
Online Access:http://dspace.nbuv.gov.ua/handle/123456789/1372
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Summary:In the article the authors present the architecture of a hardware CIL processor, which is capable to execute CIL instructions as native code. The CIL hardware engine is implemented on the top of the low-power DSP architecture, and the CIL processor has two execution cores: DSP and CIL. Such solution allows to execute both CIL and DSP instruction sets as native instructions sets and gain performance in common multimedia tasks. Therefore, the DSP-based CIL processor may be targeted for multimedia digital home and even embedded applications. The research was sponsored by RFP 2 Microsoft Corp. grant.

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