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Low-power architecture for CIL-code hardware processor
In the article the authors present the architecture of a hardware CIL processor, which is capable to execute CIL instructions as native code. The CIL hardware engine is implemented on the top of the low-power DSP architecture, and the CIL processor has two execution cores: DSP and CIL. Such solution...
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| Language: | English |
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Інститут програмних систем НАН України
2005
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| Online Access: | http://dspace.nbuv.gov.ua/handle/123456789/1372 |
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irk-123456789-13722008-10-09T18:50:26Z Low-power architecture for CIL-code hardware processor Chapyzhenka, A. Ragozin, D. Umnov, A. Інструментальні засоби і середовища програмування In the article the authors present the architecture of a hardware CIL processor, which is capable to execute CIL instructions as native code. The CIL hardware engine is implemented on the top of the low-power DSP architecture, and the CIL processor has two execution cores: DSP and CIL. Such solution allows to execute both CIL and DSP instruction sets as native instructions sets and gain performance in common multimedia tasks. Therefore, the DSP-based CIL processor may be targeted for multimedia digital home and even embedded applications. The research was sponsored by RFP 2 Microsoft Corp. grant. 2005 Article Low-power architecture for CIL-code hardware processor/ A. V. Chapyzhenka, D.V. Ragozin, A.L. Umnov // Проблеми програмування. — 2005. — N 4. — С. 20-38. — Бібліогр.: 16 назв. — англ. 1727-4907 http://dspace.nbuv.gov.ua/handle/123456789/1372 004.273 en Інститут програмних систем НАН України |
| institution |
Digital Library of Periodicals of National Academy of Sciences of Ukraine |
| collection |
DSpace DC |
| language |
English |
| topic |
Інструментальні засоби і середовища програмування Інструментальні засоби і середовища програмування |
| spellingShingle |
Інструментальні засоби і середовища програмування Інструментальні засоби і середовища програмування Chapyzhenka, A. Ragozin, D. Umnov, A. Low-power architecture for CIL-code hardware processor |
| description |
In the article the authors present the architecture of a hardware CIL processor, which is capable to execute CIL instructions as native code. The CIL hardware engine is implemented on the top of the low-power DSP architecture, and the CIL processor has two execution cores: DSP and CIL. Such solution allows to execute both CIL and DSP instruction sets as native instructions sets and gain performance in common multimedia tasks. Therefore, the DSP-based CIL processor may be targeted for multimedia digital home and even embedded applications. The research was sponsored by RFP 2 Microsoft Corp. grant. |
| format |
Article |
| author |
Chapyzhenka, A. Ragozin, D. Umnov, A. |
| author_facet |
Chapyzhenka, A. Ragozin, D. Umnov, A. |
| author_sort |
Chapyzhenka, A. |
| title |
Low-power architecture for CIL-code hardware processor |
| title_short |
Low-power architecture for CIL-code hardware processor |
| title_full |
Low-power architecture for CIL-code hardware processor |
| title_fullStr |
Low-power architecture for CIL-code hardware processor |
| title_full_unstemmed |
Low-power architecture for CIL-code hardware processor |
| title_sort |
low-power architecture for cil-code hardware processor |
| publisher |
Інститут програмних систем НАН України |
| publishDate |
2005 |
| topic_facet |
Інструментальні засоби і середовища програмування |
| url |
http://dspace.nbuv.gov.ua/handle/123456789/1372 |
| citation_txt |
Low-power architecture for CIL-code hardware processor/ A. V. Chapyzhenka, D.V. Ragozin, A.L. Umnov // Проблеми програмування. — 2005. — N 4. — С. 20-38. — Бібліогр.: 16 назв. — англ. |
| work_keys_str_mv |
AT chapyzhenkaa lowpowerarchitectureforcilcodehardwareprocessor AT ragozind lowpowerarchitectureforcilcodehardwareprocessor AT umnova lowpowerarchitectureforcilcodehardwareprocessor |
| first_indexed |
2023-03-24T08:21:41Z |
| last_indexed |
2023-03-24T08:21:41Z |
| _version_ |
1796138885667880960 |