Optimal solution in producing 32-nm CMOS technology transistor with desired leakage current

• Published in: Semiconductor Physics Quantum Electronics & Optoelectronics
• Date: 2011
• Main Authors: Elgomati, H.A., Ahmad, I., Salehuddin, F., Hamid, F.A., Zaharim, A., Majlis, B.Y., Apte, P.R.
• Format: Article
• Language: English
• Published: Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України 2011
• Online Access: https://nasplib.isofts.kiev.ua/handle/123456789/117716
• Journal Title: Digital Library of Periodicals of National Academy of Sciences of Ukraine
• Cite this: Optimal solution in producing 32-nm CMOS technology transisto with desired leakage current / H.A.Elgomati, I.Ahmad, F.Salehuddin, F.A.Hamid, A.Zaharim, B.Y.Majlis, P.R.Apte // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2011. — Т. 14, № 2. — С. 145-151 — Бібліогр.: 16 назв. — англ.

The objective of this paper is to optimize the process parameters of 32-nm
 CMOS process to get minimum leakage current. Four process parameters were chosen,
 namely: (i) source-drain implantation, (ii) source-drain compensation implantation,
 (iii) halo implantation time, and (iv) silicide annealing time. The Taguchi method
 technique was used to design the experiment. Two noise factors were used that consist of
 four measurements for each row of experiment in the L9 array, thus leading to a set of
 experiments consisting of 36 runs. The simulator of ATHENA and ATLAS were used for
 MOSFET fabrication process and electrical characterization, respectively. The results
 clearly show that the compensation implantation (46%) has the most dominant impact on
 the resulting leakage current in NMOS device, whereas source-drain (S/D) implantation
 was the second ranking factor (35%). The percent effects on signal-to-noise ratio (SNR)
 of silicide annealing temperature and halo implantation are much lower being 12% and
 7%, respectively. For the PMOS device, halo implantation was defined as an adjustment
 factor because of its minimal effect on SNR and highest on the means (43%). Halo
 implantation doping as the optimum solution for fabricating the 32-nm NMOS transistor
 is 2.38×10¹³atom/cm³. As conclusion, this experiment proves that the Taguchi analysis
 can be effectively used in finding the optimum solution in producing 32-nm CMOS
 transistor with acceptable leakage current, well within International Technology
 Roadmap for Semiconductor (ITRS) prediction.