Determination of interface state density in high-k dielectric-silicon system from conductance-frequency measurements
Capacitance-voltage (C-V ) and conductance-frequency ( G-ω ) techniques were modified in order to take into account the leakage current flowing through the metal-oxide-semiconductor (MOS) structure. The results of measurements of interface state densities in several high −k dielectric – silicon syst...
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Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України
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nasplib_isofts_kiev_ua-123456789-1182552025-06-03T16:28:47Z Determination of interface state density in high-k dielectric-silicon system from conductance-frequency measurements Gomeniuk, Yu.V. Capacitance-voltage (C-V ) and conductance-frequency ( G-ω ) techniques were modified in order to take into account the leakage current flowing through the metal-oxide-semiconductor (MOS) structure. The results of measurements of interface state densities in several high −k dielectric – silicon systems, including transition metal (Hf) and rare-earth metal (Gd, Nd) oxides, ternary compounds (LaLuO₃) and silicate (LaSiOx), are presented. It was shown that the interface state densities can be as low as ( 1.5...2) × 10¹¹ eV⁻¹cm⁻² for Al-HfO₃-Si, Pt-Gd₂O₃-Si and Pt-LaLuO₃-Si systems if the dielectric layer is deposited onto (100) silicon wafer surface. The electrically active states are attributed presumably to silicon dangling bonds at the interface between dielectric and semiconductor This work has been partly funded by the National Academy of Sciences of Ukraine in frames of the Complex Program of Fundamental Research “Nanosystems, nanomaterials and nanotechnologies”, project No.53/32/10 . Author is grateful to O. Buiu, S. Hall, M.C. Lemme, H.J. Osten, A. Laha, P.K. Hurley, K. Cherkaoui, S. Monaghan, H.D.B. Gottlob, and M. Schmidt for providing the samples for measurements, and to V.S. Lysenko and A.N. Nazarov for useful discussions and valuable comments. 2012 Article Determination of interface state density in high-k dielectric-silicon system from conductance-frequency measurements / Yu.V. Gomeniuk // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2012. — Т. 15, № 1. — С. 1-7. — Бібліогр.: 22 назв. — англ. 1560-8034 PACS 73.20.-r https://nasplib.isofts.kiev.ua/handle/123456789/118255 en Semiconductor Physics Quantum Electronics & Optoelectronics application/pdf Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України |
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Capacitance-voltage (C-V ) and conductance-frequency ( G-ω ) techniques were modified in order to take into account the leakage current flowing through the metal-oxide-semiconductor (MOS) structure. The results of measurements of interface state densities in several high −k dielectric – silicon systems, including transition metal (Hf) and rare-earth metal (Gd, Nd) oxides, ternary compounds (LaLuO₃) and silicate (LaSiOx), are presented. It was shown that the interface state densities can be as low as ( 1.5...2) × 10¹¹ eV⁻¹cm⁻² for Al-HfO₃-Si, Pt-Gd₂O₃-Si and Pt-LaLuO₃-Si systems if the dielectric layer is deposited onto (100) silicon wafer surface. The electrically active states are attributed presumably to silicon dangling bonds at the interface between dielectric and semiconductor |
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Gomeniuk, Yu.V. Determination of interface state density in high-k dielectric-silicon system from conductance-frequency measurements Semiconductor Physics Quantum Electronics & Optoelectronics |
| author_facet |
Gomeniuk, Yu.V. |
| author_sort |
Gomeniuk, Yu.V. |
| title |
Determination of interface state density in high-k dielectric-silicon system from conductance-frequency measurements |
| title_short |
Determination of interface state density in high-k dielectric-silicon system from conductance-frequency measurements |
| title_full |
Determination of interface state density in high-k dielectric-silicon system from conductance-frequency measurements |
| title_fullStr |
Determination of interface state density in high-k dielectric-silicon system from conductance-frequency measurements |
| title_full_unstemmed |
Determination of interface state density in high-k dielectric-silicon system from conductance-frequency measurements |
| title_sort |
determination of interface state density in high-k dielectric-silicon system from conductance-frequency measurements |
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Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України |
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2012 |
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https://nasplib.isofts.kiev.ua/handle/123456789/118255 |
| citation_txt |
Determination of interface state density in high-k dielectric-silicon system from conductance-frequency measurements / Yu.V. Gomeniuk // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2012. — Т. 15, № 1. — С. 1-7. — Бібліогр.: 22 назв. — англ. |
| series |
Semiconductor Physics Quantum Electronics & Optoelectronics |
| work_keys_str_mv |
AT gomeniukyuv determinationofinterfacestatedensityinhighkdielectricsiliconsystemfromconductancefrequencymeasurements |
| first_indexed |
2025-12-02T06:42:43Z |
| last_indexed |
2025-12-02T06:42:43Z |
| _version_ |
1850377779341688832 |
| fulltext |
Semiconductor Physics, Quantum Electronics & Optoelectronics, 2012. V. 15, N 1. P. 1-7.
© 2012, V. Lashkaryov stitute of Semiconductor Physics, Nationa y of Sciences of Ukraine
1
In l Academ
PACS 73.20.-r
Determination of interface state density in high-k dielectric-silicon
system from conductance-frequency measurements
Yu.V. Gomeniuk
V. Lashkaryov Institute of Semiconductor Physics, NAS of Ukraine, 03028 Kyiv, Ukraine
E-mail: yurigom@lab15.kiev.ua
Abstract. Capacitance-voltage ( C-V ) and conductance-frequency ( ) techniques
were modified in order to take into account the leakage current flowing through the
metal-oxide-semiconductor (MOS) structure. The results of measurements of interface
state densities in several high
ωG-
k− dielectric – silicon systems, including transition metal
(Hf) and rare-earth metal (Gd, Nd) oxides, ternary compounds (LaLuO3) and silicate
(LaSiOx), are presented. It was shown that the interface state densities can be as low as
( ) 2111 cmeV102...5.1 −−× for Al-HfO2-Si, Pt-Gd2O3-Si and Pt-LaLuO3-Si systems if the
dielectric layer is deposited onto (100) silicon wafer surface. The electrically active states
are attributed presumably to silicon dangling bonds at the interface between dielectric
and semiconductor.
Keywords: high-k dielectric, dielectric-semiconductor interface.
Manuscript received 17.11.11; revised manuscript received 21.12.11; accepted for
publication 26.01.12; published online 29.02.12.
1. Introduction
Dielectrics with a high dielectric constant (high k−
dielectrics) are currently considered as a replacement of
silicon dioxide in complementary metal-oxide-
semiconductor (CMOS) technology. The continuing
downscaling of MOS devices requires respective
thinning of gate dielectrics. However, the reduction of
SiO2 thickness below 1.5 nm is associated with several
critical drawbacks, the most important of which is an
increased leakage current through the gate oxide. In
order to reduce gate leakage while maintaining the gate
capacitance, dielectrics with higher permittivity than
SiO2, the so-called high k− dielectrics, are being
intensively investigated now. High dielectrics can be
grown thicker than silicon oxide providing the same
capacitance equivalent thickness (CET) and offering
significant gate leakage reduction due to suppressing the
direct tunneling effects.
k−
Transition metal and rare-earth metal oxides are
considered as perspective high materials to replace
silicon dioxide for future CMOS technology because of
their wide bandgap and large offsets between
conductance and valence bands of dielectric and silicon.
Among the high
k−
k− dielectrics, HfO2 is the most
promising candidate because of its relatively high
dielectric constant, large bandgap, and thermal stability.
The comprehensive reviews of future high − dielectrics
for substitution of silicon dioxide can be found in
[1
k
4 k− ]. The electrical properties of the high −
oxide/silicon structures, such as leakage current and
band offsets, were found to depend also on the chemical
composition of the transition layer at the interface [5].
The use of epitaxially grown single-crystalline thin
layers of rare-earth oxide dielectric allows us to solve
two problems: first, to reduce thickness of the transition
layer between silicon and high dielectric [6] and,
second, to decrease the leakage current through grain
boundaries that are generated during crystallization of
the amorphous dielectric layer at high-temperature
technological processes [7].
k−
The investigations of interface states are of interest,
first of all, because low densities of the interface states
are required to provide an appropriate channel mobility
of CMOS devices and to guarantee the precise control of
the surface potential under the gate. However, even with
the perfect crystalline quality of the dielectric layer and
abrupt oxide/silicon interface, the achievement of low
Semiconductor Physics, Quantum Electronics & Optoelectronics, 2012. V. 15, N 1. P. 1-7.
Table. Parameters of the samples.
Sample # Oxide layer Substrate Forming gas annealing Thickness, nm CET,
nm
k
1 Gd2O3 pSi (111) 500 °C/10 min 6.7 2.35 11.2
2 Gd2O3 pSi (100) 450 °C/10 min 7.5 2.5 11.7
3 Gd2O3 pSi (111) 450 °C/10 min 13.2 4.5 11.5
4 Nd2O3 pSi (111) 450 °C/10 min 10.0 3.2 11.9
leakage currents in high dielectric – silicon systems
is a problem, because the rare-earth oxides, like to most
of types of high dielectrics, are ionic compounds
with relatively weak chemical bonds between ions, and
are known to contain a high concentration of oxygen
vacancies [1]. These intrinsic defects produce the local
energy levels in the bandgap, being a reason of relatively
high leakage currents. In this case, the charge carrier
exchange between the dielectric and semiconductor
essentially depends on the presence and density of
surface states at the interface. This is the second reason
why the studies of properties inherent to the interface
states in the high dielectric – semiconductor system
are of interest.
k−
k−
k−
Application of conductance-frequency spectroscopy
to characterization of high -oxide/silicon interface and
possible nature of interface defects of several high
k−
k−
systems were discussed in [4, 8–10]. However, this
technique was not commonly used for the study of
interface properties in the case when a high leakage
current flows through the dielectric film. In this paper, the
measurement technique was modified to account for
possible leakage currents. This paper presents the results
of capacitance-voltage and ac conductance-frequency
measurements for several high dielectrics, including
transition metal (Hf) and rare-earth metal (Gd, Nd) oxides,
ternary compounds (LaLuO
k−
3) and silicate (LaSiOx),
epitaxially grown on silicon substrates.
2. Experimental
The HfO2 films were deposited on fresh un-etched p-
type Si(100) substrate with the resistivity of
. Films were deposited at 500 °C by
liquid injection MOCVD, using the Aixtron AIX 200FE
Atomic Vapour Deposition (AVD) reactor fitted with the
“Trijet”™ injector system. The hafnium precursor was
Hf(mmp)
cmOhm01...1 ⋅
4. The wafers were HF cleaned before the
deposition. The metal gate electrodes were deposited by
sputtering to fabricate MIS capacitors. The nitride gates
were reactively sputtered in Ar/N flow, the silicidation
process of the NiSi gate was performed in argon at
500 °C for 10 s. The thickness of metal and metal
compound layers was 50 nm. The standard lift-off
process was used to pattern the conducting films to
define the circular dots. Then the samples were annealed
in forming gas at 400 °C for 30 min. The samples with
four different gate materials, NiAlN, TiN, NiSi, and Al,
were investigated.
The single-crystalline Gd and Nd oxide films were
grown in an integrated multichamber ultrahigh vacuum
system using solid source molecular beam epitaxy
(MBE), which allows better control of
semiconductor/dielectric interface properties and to
avoid a low dielectric constant interfacial layer. The
details of deposition of metal oxide dielectric films can
be found elsewhere [14]. Prior to Pt metal dot
deposition, the structures were annealed in forming gas
for 10 min at 450 or 500 °C to decrease the charge
instability in dielectrics [14]. Four different structures
were studied: Pt-Gd2O3-pSi(111) annealed at 500 °C
(hereafter denoted as #1), Pt-Gd2O3-pSi(100) annealed at
450 °C (#2), Pt-Gd2O3-pSi(111) annealed at 450 °C (#3),
and Pt-Nd2O3-pSi(111) annealed at 450 °C (#4). The
chemical composition of dielectric layers, details of their
preparation and some parameters are shown in Table.
The dielectric layers in the Pt-LaLuO3-pSi(100)
MOS structures were deposited by molecular beam
deposition (MBD). Evaporation of La and Lu in O2 was
performed at a substrate temperature of 450 °C. Two
structures were studied with the nominal physical
thicknesses of the dielectric layer (LaLuO3) of tox =
6.5 nm and 20 nm. The samples were exposed to
forming gas annealing at 400 °C for 10 min (10% H2). Pt
gates were prepared by e-gun evaporation through a
shadow mask.
The dielectric layers of the NiSi-LaSiOx-Si(100)
MOS structures were deposited onto n- and p-type
silicon substrates by electron beam evaporation from
La2O3 pellets [5]. The structures were studied with the
nominal physical thicknesses of the dielectric layer
(LaSiOx) of tox = 10 nm and 7.5 nm. Circular NiSi
electrodes have been fabricated by full silicidation and
reactive ion etching [6]. The samples obtained no post-
metallization annealing treatment.
MOS capacitors were characterized by capacitance-
voltage ( ), conductance vs. frequency (C-V ωG- )
measurements within the temperature range 120 up to
320 K using an Agilent 4284A LCR meter.
© 2012, V. Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine
2
Semiconductor Physics, Quantum Electronics & Optoelectronics, 2012. V. 15, N 1. P. 1-7.
© 2012, V. Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine
3. Measurement techniques
One of general problems in characterization of
ultra-thin SiO
C-V
2 and alternative dielectric layers is a large
leakage current, leading to the appearance of parasitic
resistance of back contact and semiconductor bulk.
These effects lead to underestimation of the true
capacitance in accumulation region, if the curve is
measured in the parallel mode [11, 12]. The correct
dependence can be extracted from C-V data measured
at two different frequencies using the approach
described in [13]. In this case, the resistance is given by:
C-V
C-V
2222 )1(
1
CDCC
Rp
ωω −′+′
= , (1)
where
CR
D
′′
=′
ω
1
, R′ and are measured
resistance and capacitance, respectively, and the
corrected capacitance equals:
C′
2
2
2
1
2
22
2
2
2
11
2
1 )1()1(
ff
DCfDCf
C
−
′+′−′+′
= . (2)
Here, subscripts 1 and 2 denote two different
measuring frequencies. For the case of measurements at
two frequencies in the series mode respective equations
can be modified as follows:
2
2
2
1
2
2
21
2
1
ff
CfCf
C ss
−
′−′
= . (3)
The interface state density was determined from the
conductance-frequency measurements using the classical
approach of Nicollian and Goetzberger [14, 15]. This
technique proved its effectiveness and precision and has
become a standard for studying the electrically active
states at the dielectric/semiconductor interface for at
least last four decades. However, it was primarily
developed for the SiO2/Si systems with a relatively thick
dielectric layer and relatively low leakage currents. The
comprehensive analysis of advantages and restrictions of
the ωG- technique, in particular in its application to
measurements of interface states in the structures with
high k− dielectrics, can be found in [9, 10].
Fig. 1 presents the equivalent circuits suggested for
modeling the processes and for extracting the density of
states from the measured admittance of the total MOS
system. Fig. 1a shows the circuit consisting of the
measured capacitance Cm and conductance Gm,
connected in parallel, just as it is assumed by the LCR-
meter to be placed between its testing leads. Nicollian
and Goetzberger suggested that MOS structure can be
represented by the circuit with the oxide capacitance Cox,
the capacitance of the depletion layer of semiconductor
Cs, and the capacitance Cit and conductance Git of the
interface states connected as shown in Fig. 1b [14]. In
this case, from the measured dependence of the sample
conductance G on circular frequency ω of the small ac
testing voltage, the concentration of interface states can
be determined directly from the peak value of G/ω vs. ω
dependence. Fig. 1c shows the equivalent circuit
suggested in [9, 10] where some principal remarks were
made concerning the interpretation of the results in the
case when the density of states or capture cross section
has strong energy dependence. However, none of these
equivalent circuits takes into consideration the fact that
the dielectric layer itself may have significant leakage
current, which becomes more important if the thickness
of the oxide is small. Therefore, we suggest that an
additional oxide conductance Gox should be included
into the equivalent circuit as shown in Fig. 1d. Even
without writing the cumbersome equations describing
the total impedance of this circuit, it is clear that the
upper RC-circuit at some parameters may give similar
contribution to the total measured capacitance and
conductance, as the lower one. This may lead to
ambiguity in determination of parameters of the
interface states, or even to mistaken assignment of the
oxide bulk effects to the interface-related processes.
In the case of dielectric layers with leakage
currents, the results of both C-V and ωG-
Fig. 1. Equivalent circuits: a) with circuit elements as measured, b) suggested by Nicollian and Goetzberger, c) suggested by
J. Piscator et al., and d) with the oxide conductivity included.
3
Semiconductor Physics, Quantum Electronics & Optoelectronics, 2012. V. 15, N 1. P. 1-7.
measurements require correction, as described in [16].
Before the conductance related to interface traps is
plotted in G/ω vs. frequency coordinates, the dc
conductance (or the conductance at the minimum
frequency) should be subtracted from the measured
value in order to get rid of the current component due to
leakage through the dielectric layer. The similar
approach is used also for studying the distribution of
defects in semiconductor heterojunctions by using the
admittance technique [17].
4. Results and discussion
Polysilicon has been the gate electrode of the transistor
technology for several decades, however, the gate
depletion problem becomes a major drawback for its
further application. In addition, reaction between the
polysilicon gate and high k− dielectric can produce
silicides, which affects the dielectric integrity of the gate
stack. These reasons justify the investigation of metal
and metallic compounds as gate electrodes for CMOS
devices.
The distribution of interface traps for the samples
with HfO2 dielectric and three different gate materials
(NiAlN, TiN, NiSi) is shown in Fig. 2. The spectrum of
interface states is similar for these samples increasing
from in the depth of the bandgap up to
closer to the valence band
edge. The difference of the gate materials affects mainly
the part of the distribution near the bandgap edge. The
lowest D
2111 cmeV103 −−×
( ) 2112 cmeV105.5...5.3 −−×
it values were observed for NiAlN gate, and the
highest – for the TiN gate. Completely different behavior
of the distribution of interface states was found for Al-
HfO2-Si structure, as shown in Fig. 3. In this case, the
peak of the Dit distribution is observed with a maximum at
EV+0.19 eV and with much lower value of the interface
trap density, than for other samples at the same energy
position. Such a distribution can be attributed to the
presence of a local state within the bandgap. The
temperature dependence of the capture cross-section for
the respective trap is plotted in the inset to Fig. 3.
0.0 0.1 0.2 0.3
0
1x1012
2x1012
3x1012
4x1012
5x1012
220 K
D
it, e
V
-1
cm
-2
E-EV , eV
TiN
NiAlN
NiSi
© 2012, V. Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine
Fig. 2. Interface state spectra for three samples with HfO2
dielectric and different gate electrodes measured at 220 K.
0.15 0.20 0.25
0
1x1011
2x1011
180 200 220
4.0x10-17
8.0x10-17
1.2x10-16
1.6x10-16
D
it, e
V
-1
cm
-2
E-EV , eV
220 K
200 K
Al-HfO2-Si
σ, cm2
T, K
Fig. 3. Interface state spectra for Al-HfO2-Si structure
measured at 200 and 220 K. The inset shows the temperature
dependence of the trap capture cross-section.
0.0 0.1 0.2 0.3 0.4 0.5 0.6
0.0
2.0x1011
4.0x1011
6.0x1011
8.0x1011
Pb0 (x5)
Gd2O3-Si(111),500oC
Gd2O3-Si(100),450oC
Gd2O3-Si(111),450oC
Nd2O3-Si(111),450oC
D
it, e
V
-1
cm
-2
E-EV , eV
300K
Pb1 (x5)
Fig. 4. Interface state density for four samples calculated from
G - ω measurements and bandgap distribution of Pb centers on
oxidized (100) Si wafer.
Fig. 4 shows the interface state density distribution
over the lower part of the bandgap for four samples with
Gd and Nd oxide dielectric layers, determined by the
standard conductance-frequency ( ) technique with
subtraction of leakage currents at low frequency. It can
be seen that the lowest values are observed on the Gd
ωG-
2O3
layer on Si(100) substrate (sample #2), where the
average concentration of interface states in the studied
energy interval equals to . The highest
values are observed in the Nd
2110 cmeV105 −−×
2O3 film, possibly due to a
larger lattice mismatch at the interface between the
dielectric and semiconductor. Annealing at 500 °C
reduces the interface state density by a factor of 2, as
compared to that at 450 °C for Gd2O3 oxide grown on
Si(111) substrate. It should be noted that the maximum
concentration of the interface states is observed around
Et = EV+0.20 eV and, in dependence on orientation of Si
wafer, around EV+0.40 eV for Si (100) and EV+0.30 eV
for Si (111). The surface traps with such energy
distribution were observed in the SiO2/Si interface
4
Semiconductor Physics, Quantum Electronics & Optoelectronics, 2012. V. 15, N 1. P. 1-7.
[18, 19], and the maximum concentration at EV+0.40 eV
was associated with a mixture of Pb0 and Pb1 centers and
that at EV+0.30 eV – with Pb0 centers [20]. Energy
distributions of these centers taken from [20] are also
depicted in Fig. 4. The concentration of interface states
in the (100) silicon surface is much lower than that for
(111) surface, the same as it is observed in Si-SiO2
system, which can be considered as another evidence of
formation of intermediate transition region SiOx between
silicon and high dielectric. Such an interfacial region
can be formed under the high
k−
k− oxide due to diffusion
of oxygen through the oxide during the deposition
process [1]. The lower values of the interface state
density for the film grown on Si(100), the significant
reduction of Dit by higher-temperature forming gas
annealing and the higher values of Dit for the oxide with
larger lattice mismatch enabled us to suggest silicon
dangling bond centers as the dominant interface states
for the high /silicon structures under study. However,
the presence of shallower traps may be attributed to the
effect of the rare-earth ions on the structure of the
transition layer.
k−
Fig. 5 shows the interface density distribution over
the lower part of the bandgap for Pt-LaLuO3-Si
structures with 6.5 and 20 nm thick dielectric layers. The
interface state density is lower for the sample with the
thicker oxide, reflecting a better quality of the interface,
probably due to presence of a thicker interfacial silicate
layer. Typical maxima in the interface state distributions
for MOS structures (1.2×1011 and )
were found at about 0.25–0.3 eV from the silicon
valence band edge.
2111 cmeV105.2 −−×
Fig. 6 shows the distribution of interface state
density over silicon bandgap for both n- and p-type
samples with 10 nm LaSiOx dielectric layer. The middle
region corresponds to the values extracted from the
conductance technique, while the Dit distribution near
the edges of bandgap was obtained using the Gray-
Brown technique [21]. It should be noted that the two
separate approaches yield values of Dit which are in
good agreement in the energy ranges where these two
methods overlap.
0.25 0.30 0.35 0.40 0.45 0.50
0.0
0.5
1.0
1.5
2.0
2.5
3.0
tox, nm
6.5
20
Pt-LaLuO3-pSi(100)
D
it, 1
011
e
V
-1
cm
-2
E-EV , eV
Fig. 5. Interface state density for LaLuO3-Si structures.
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0
1
2
3
4
5
6
7
8
G-ω method:
Gray-Brown:
NiSi / LaSiOx / Si
D
it, 1
011
e
V
-1
cm
-2
E-EV , eV
Fig. 6. Interface state density distribution over the silicon
bandgap determined using the conductance and Gray-Brown
methods.
The maximum values of interface state density
were found to be about at 0.2 eV
above the Si valence band edge and
at 0.34 eV below the Si conduction band edge. These
high values could be expected because no post-
metallization annealing was performed. The effective
trap cross-sections were found to be equal to
and for traps related to the maxima of D
2111 cmeV106.4 −−×
2111 cmeV109.7 −−×
16103.1 −×
216 cm103.2 −× it
distribution near the valence and conduction bands,
respectively. The energy distribution is slightly different
from that for Pb0/Pb1 defects, which shows up two
maxima at EV+0.25 eV and EV+0.83 eV, respectively [4].
It is evident from the presented data that not all of
high k− dielectrics under study can approach silicon
dioxide in terms of interface states density values. The
interface state densities of around
( ) 2111 cmeV102...5.1 −−× were observed in Al-HfO2-Si,
Pt-Gd2O3-Si and Pt-LaLuO3-Si systems in the case when
the dielectric layer is deposited onto (100) silicon wafer
surface. Although these values are still an order of
magnitude higher than the best values achieved in SiO2-
Si structures, the operability of MOS transistors with
high k− dielectrics was recently demonstrated even for a
novel ternary LaLuO3 oxide [22]. The interface state
density for LaSiOx dielectric is relatively high, but
evidently it can be substantially improved by using the
forming gas annealing.
The physical nature of surface states at the high k−
dielectric – semiconductor interface is still being
debated. In addition to silicon dangling bonds, oxygen
vacancy inside the high k− oxide, isolated metal atom in
the interlayer, or the metal atom bonded to silicon
substrate can also make a contribution to the measured
interface state density [4]. But the energy position of
peaks in the interface state distribution and similarity of
the spectra for different high oxides allow to make a
conclusion that the main defects responsible for
k−
© 2012, V. Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine
5
Semiconductor Physics, Quantum Electronics & Optoelectronics, 2012. V. 15, N 1. P. 1-7.
formation of electrically active states at the interface are
silicon dangling bonds. Slight differences in position and
broadening of the experimental distributions as
compared to the theoretical line for a monoenergetic
level is explained by variations in defect bond angles
and by the presence of strain at the interface.
5. Conclusions
Thus, it was shown that the conventional and C-V ωG-
techniques can be modified for account of a leakage
current through the dielectric layer and then successfully
used for the measurement of the interface state
distribution in high dielectric – semiconductor
systems. Features of the interface state spectra for
different high compounds, including transition metal
and rare earth metal oxides, ternary oxide LaLuO
k−
k−
3 and
rare earth metal silicate LaSiOx, prove that the
electrically active states at the interface between
dielectric and semiconductor are mainly due to silicon
dangling bonds.
Acknowledgements
This work has been partly funded by the National
Academy of Sciences of Ukraine in frames of the
Complex Program of Fundamental Research
“Nanosystems, nanomaterials and nanotechnologies”,
project No.53/32/10 . Author is grateful to O. Buiu,
S. Hall, M.C. Lemme, H.J. Osten, A. Laha, P.K. Hurley,
K. Cherkaoui, S. Monaghan, H.D.B. Gottlob, and
M. Schmidt for providing the samples for measurements,
and to V.S. Lysenko and A.N. Nazarov for useful
discussions and valuable comments.
H−
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