ОПТОЕЛЕКТРОННИЙ СУМАТОР-ПОМНОЖУВАЧ ДЛЯ РЕАЛІЗАЦІЇ АЛГОРИТМУ DMAC
Mathematical model of the iterative process of solving systems of linear equations in which the input coefficient array is divided into machining hardware arrays bit partial sums and the corresponding bitwise shifts, which allows to calculate in parallel the operators of sum and shift. The architect...
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| Datum: | 2017 |
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| Hauptverfasser: | , , |
| Format: | Artikel |
| Sprache: | Russian |
| Veröffentlicht: |
Vinnytsia National Technical University
2017
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| Schlagworte: | |
| Online Zugang: | https://oeipt.vntu.edu.ua/index.php/oeipt/article/view/448 |
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| Назва журналу: | Optoelectronic Information-Power Technologies |
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Optoelectronic Information-Power Technologies| Zusammenfassung: | Mathematical model of the iterative process of solving systems of linear equations in which the input coefficient array is divided into machining hardware arrays bit partial sums and the corresponding bitwise shifts, which allows to calculate in parallel the operators of sum and shift. The architecture optoelectronic matrix adder-multiplier for the implementation of calculations according to the model by the algorithm of the interim summation of DMAC is proposed. Improved model element of the array SS-VSCEL with external optical emission in the cavity as a basic element of SLM for optical linear algebraic processor is investigated. |
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