Контролепригодная схема двоичного сумматора на основе 16-разрядной группы секций
A testable functional‑logical circuit of a binary adder based on a 16‑bit group of 4‑bit sections is considered. The design provides simultaneous carry propagation within each section and section group, and sequential carry propagation between groups. The circuit was developed within the concept of...
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| Datum: | 2003 |
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| 1. Verfasser: | |
| Format: | Artikel |
| Sprache: | Ukrainisch |
| Veröffentlicht: |
PE "Politekhperiodika", Book and Journal Publishers
2003
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| Schlagworte: | |
| Online Zugang: | https://www.tkea.com.ua/index.php/journal/article/view/TKEA2003.1.21 |
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| Назва журналу: | Technology and design in electronic equipment |
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