Топологическая обработка информации системами искусственного интеллекта при решении логических задач
A new method for implementing parallel logic gates is described. The realization of parallel logic for two-gradation patterns is considered based on topological information processing (TIP), which is also used in the recognition of visual images by single-layer artificial intelligence systems. Esti...
Gespeichert in:
| Datum: | 2008 |
|---|---|
| Hauptverfasser: | , |
| Format: | Artikel |
| Sprache: | Ukrainisch |
| Veröffentlicht: |
PE "Politekhperiodika", Book and Journal Publishers
2008
|
| Schlagworte: | |
| Online Zugang: | https://www.tkea.com.ua/index.php/journal/article/view/TKEA2008.2.21 |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| Назва журналу: | Technology and design in electronic equipment |
Institution
Technology and design in electronic equipment| Zusammenfassung: | A new method for implementing parallel logic gates is described. The realization of parallel logic for two-gradation patterns is considered based on topological information processing (TIP), which is also used in the recognition of visual images by single-layer artificial intelligence systems. Estimates of the main parameters of TIP devices are provided, showing that their performance can reach 1016 operations per second, while the number of structural elements is significantly smaller than that of known optoelectronic logic devices.
|
|---|