Оптимизация изготовления высоковольтного горизонтального р-канального МОП-транзистора
Simulation of semiconductor structures provides an opportunity to reduce manufacturing costs and optimize the parameters of integrated circuit elements and devices. To design integrated circuits with specified properties, it is necessary to obtain the required electrical characteristics of the circu...
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| Date: | 2006 |
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| Main Authors: | , , , |
| Format: | Article |
| Language: | Ukrainian |
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PE "Politekhperiodika", Book and Journal Publishers
2006
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| Online Access: | https://www.tkea.com.ua/index.php/journal/article/view/TKEA2006.4.45 |
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| Journal Title: | Technology and design in electronic equipment |
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Technology and design in electronic equipment| _version_ | 1861862057549234176 |
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| author | Leonov, N. I. Lemeshevskaya, A. M. Dudar, N. L. Getzman, S. N. |
| author_facet | Leonov, N. I. Lemeshevskaya, A. M. Dudar, N. L. Getzman, S. N. |
| author_sort | Leonov, N. I. |
| baseUrl_str | https://www.tkea.com.ua/index.php/journal/oai |
| collection | OJS |
| datestamp_date | 2026-04-07T20:24:14Z |
| description | Simulation of semiconductor structures provides an opportunity to reduce manufacturing costs and optimize the parameters of integrated circuit elements and devices. To design integrated circuits with specified properties, it is necessary to obtain the required electrical characteristics of the circuit elements. This paper presents the results of optimization simulation of the technological route and electrical characteristics of a high-voltage lateral p-channel MOS transistor, which has a threshold voltage of 0.8–1.8 V, a drain-source breakdown voltage above 80 V, and an on-state drain current exceeding 0.5 mA at a gate voltage of 5 V. The simulated technological route of the PMOS transistor includes n-type epitaxial film growth on a p-type substrate, polysilicon gate formation, p-type drain region formation, p+ source and drain region formation, intermediate oxide deposition, and metal deposition. The transistor’s I–V characteristics were obtained from calculations considering variations in epitaxial film specific resistance (ρv) and gate oxide thickness (d). The tendencies of threshold voltage changes of the PMOS transistor were identified as a result of simulation in accordance with ρv and d variations. Experimental samples were fabricated in epitaxial films with different values of ρv and d. Comparison of experimental data with simulation results allowed determination of the most acceptable values of ρv and d (taking into account production conditions), ensuring the required threshold voltage of the analyzed transistor. |
| first_indexed | 2026-04-08T01:00:24Z |
| format | Article |
| id | oai:tkea.com.ua:article-942 |
| institution | Technology and design in electronic equipment |
| keywords_txt_mv | keywords |
| language | Ukrainian |
| last_indexed | 2026-04-08T01:00:24Z |
| publishDate | 2006 |
| publisher | PE "Politekhperiodika", Book and Journal Publishers |
| record_format | ojs |
| spelling | oai:tkea.com.ua:article-9422026-04-07T20:24:14Z Optimization of the fabrication process of a high-voltage lateral p-channel MOS transistor Оптимизация изготовления высоковольтного горизонтального р-канального МОП-транзистора Leonov, N. I. Lemeshevskaya, A. M. Dudar, N. L. Getzman, S. N. PMOS transistor fabrication process simulation рМОП-транзистор технологический маршрут моделирование Simulation of semiconductor structures provides an opportunity to reduce manufacturing costs and optimize the parameters of integrated circuit elements and devices. To design integrated circuits with specified properties, it is necessary to obtain the required electrical characteristics of the circuit elements. This paper presents the results of optimization simulation of the technological route and electrical characteristics of a high-voltage lateral p-channel MOS transistor, which has a threshold voltage of 0.8–1.8 V, a drain-source breakdown voltage above 80 V, and an on-state drain current exceeding 0.5 mA at a gate voltage of 5 V. The simulated technological route of the PMOS transistor includes n-type epitaxial film growth on a p-type substrate, polysilicon gate formation, p-type drain region formation, p+ source and drain region formation, intermediate oxide deposition, and metal deposition. The transistor’s I–V characteristics were obtained from calculations considering variations in epitaxial film specific resistance (ρv) and gate oxide thickness (d). The tendencies of threshold voltage changes of the PMOS transistor were identified as a result of simulation in accordance with ρv and d variations. Experimental samples were fabricated in epitaxial films with different values of ρv and d. Comparison of experimental data with simulation results allowed determination of the most acceptable values of ρv and d (taking into account production conditions), ensuring the required threshold voltage of the analyzed transistor. По результатам моделирования определены тенденции изменения порогового напряжения р-канального МОП-транзистора в соответствии с изменениями удельного сопротивления эпитаксиальной пленки ρv и толщины подзатворного окисла d. Получены экспериментальные образцы в эпитаксиальных пленках с различными значениями ρv и d. Определены наиболее приемлемые (с учетом условий производства) значения ρv и d, позволяющие получить требуемые значения порогового напряжения исследуемого транзистора. PE "Politekhperiodika", Book and Journal Publishers 2006-08-31 Article Article Peer-reviewed Article application/pdf https://www.tkea.com.ua/index.php/journal/article/view/TKEA2006.4.45 Technology and design in electronic equipment; No. 4 (2006): Tekhnologiya i konstruirovanie v elektronnoi apparature; 45-47 Технологія та конструювання в електронній апаратурі; № 4 (2006): Технология и конструирование в электронной аппаратуре; 45-47 3083-6549 3083-6530 uk https://www.tkea.com.ua/index.php/journal/article/view/TKEA2006.4.45/854 Copyright (c) 2006 N. I. Leonov, A. M. Lemeshevskaya, N. L. Dudar, S. N. Getzman http://creativecommons.org/licenses/by/4.0/ |
| spellingShingle | рМОП-транзистор технологический маршрут моделирование Leonov, N. I. Lemeshevskaya, A. M. Dudar, N. L. Getzman, S. N. Оптимизация изготовления высоковольтного горизонтального р-канального МОП-транзистора |
| title | Оптимизация изготовления высоковольтного горизонтального р-канального МОП-транзистора |
| title_alt | Optimization of the fabrication process of a high-voltage lateral p-channel MOS transistor |
| title_full | Оптимизация изготовления высоковольтного горизонтального р-канального МОП-транзистора |
| title_fullStr | Оптимизация изготовления высоковольтного горизонтального р-канального МОП-транзистора |
| title_full_unstemmed | Оптимизация изготовления высоковольтного горизонтального р-канального МОП-транзистора |
| title_short | Оптимизация изготовления высоковольтного горизонтального р-канального МОП-транзистора |
| title_sort | оптимизация изготовления высоковольтного горизонтального р-канального моп-транзистора |
| topic | рМОП-транзистор технологический маршрут моделирование |
| topic_facet | PMOS transistor fabrication process simulation рМОП-транзистор технологический маршрут моделирование |
| url | https://www.tkea.com.ua/index.php/journal/article/view/TKEA2006.4.45 |
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