An analytical accumulation mode SOI pMOSFET model for high-temperature analog applications

An analytical accumulation mode SOI pMOSFET model for high-temperature analog applications

An accumulation mode SOI pMOSFET model for simulation of analog circuits meant for high-temperature applications is presented in the paper. The model is based on explicit expressions for the drain current with an infinite order of continuity what assures smooth transitions between different operatio...

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Published in:Semiconductor Physics Quantum Electronics & Optoelectronics
Date:2006
Main Authors: Houk, Yu., Iniguez, B., Flandre, D., Nazarov, A.
Format: Article
Language:English
Published: Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України 2006
Online Access:https://nasplib.isofts.kiev.ua/handle/123456789/121592
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Cite this:An analytical accumulation mode SOI pMOSFET model for high-temperature analog applications / Yu. Houk, B. Iniguez, D. Flandre, A. Nazarov // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2006. — Т. 9, № 1. — С. 43-54. — Бібліогр.: 15 назв. — англ.

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Digital Library of Periodicals of National Academy of Sciences of Ukraine
id nasplib_isofts_kiev_ua-123456789-121592
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spelling Houk, Yu.
Iniguez, B.
Flandre, D.
Nazarov, A.
2017-06-14T17:29:50Z
2017-06-14T17:29:50Z
2006
An analytical accumulation mode SOI pMOSFET model for high-temperature analog applications / Yu. Houk, B. Iniguez, D. Flandre, A. Nazarov // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2006. — Т. 9, № 1. — С. 43-54. — Бібліогр.: 15 назв. — англ.
1560-8034
PACS 85.30.Tv, 85.30.De
https://nasplib.isofts.kiev.ua/handle/123456789/121592
An accumulation mode SOI pMOSFET model for simulation of analog circuits meant for high-temperature applications is presented in the paper. The model is based on explicit expressions for the drain current with an infinite order of continuity what assures smooth transitions between different operation regimes of the transistor. This model is valid for all regimes of normal operation, demonstrates proper description of high-temperature behavior of the subthreshold and off-state current. The model characteristics show a good agreement with the experimental data for temperatures up to 300 °C.
The work was performed in the frame of SPRING project (project #IST-1999-12342), and also was partially supported by NATO CLG (PST CLG 979999). The authors are thankful to T.E. Rudenko, V. Kilchytska and A. Tuor for helpful discussions.
en
Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України
Semiconductor Physics Quantum Electronics & Optoelectronics
An analytical accumulation mode SOI pMOSFET model for high-temperature analog applications
Article
published earlier
institution Digital Library of Periodicals of National Academy of Sciences of Ukraine
collection DSpace DC
title An analytical accumulation mode SOI pMOSFET model for high-temperature analog applications
spellingShingle An analytical accumulation mode SOI pMOSFET model for high-temperature analog applications
Houk, Yu.
Iniguez, B.
Flandre, D.
Nazarov, A.
title_short An analytical accumulation mode SOI pMOSFET model for high-temperature analog applications
title_full An analytical accumulation mode SOI pMOSFET model for high-temperature analog applications
title_fullStr An analytical accumulation mode SOI pMOSFET model for high-temperature analog applications
title_full_unstemmed An analytical accumulation mode SOI pMOSFET model for high-temperature analog applications
title_sort analytical accumulation mode soi pmosfet model for high-temperature analog applications
author Houk, Yu.
Iniguez, B.
Flandre, D.
Nazarov, A.
author_facet Houk, Yu.
Iniguez, B.
Flandre, D.
Nazarov, A.
publishDate 2006
language English
container_title Semiconductor Physics Quantum Electronics & Optoelectronics
publisher Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України
format Article
description An accumulation mode SOI pMOSFET model for simulation of analog circuits meant for high-temperature applications is presented in the paper. The model is based on explicit expressions for the drain current with an infinite order of continuity what assures smooth transitions between different operation regimes of the transistor. This model is valid for all regimes of normal operation, demonstrates proper description of high-temperature behavior of the subthreshold and off-state current. The model characteristics show a good agreement with the experimental data for temperatures up to 300 °C.
issn 1560-8034
url https://nasplib.isofts.kiev.ua/handle/123456789/121592
citation_txt An analytical accumulation mode SOI pMOSFET model for high-temperature analog applications / Yu. Houk, B. Iniguez, D. Flandre, A. Nazarov // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2006. — Т. 9, № 1. — С. 43-54. — Бібліогр.: 15 назв. — англ.
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fulltext Semiconductor Physics, Quantum Electronics & Optoelectronics, 2006. V. 9, N 1. P. 43-54. © 2006, V. Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine 43 PACS 85.30.Tv, 85.30.De An analytical accumulation mode SOI pMOSFET model for high-temperature analog applications Yuri Houk1*, Benjamin Iñiguez2, Denis Flandre3, Alexei Nazarov1 1V. Lashkaryov Institute of Semiconductor Physics, NAS of Ukraine 41, prospect Nauky, 03028 Kyiv, Ukraine 2Universitat Rovira i Virgili (URV), Av. Països Catalans 26, Campus Sescelades, 43007 Tarragona (Catalonia), Spain 3Université Catholique de Louvain (UCL), Bâtiment Maxwell, Place du Levant 3, B-1348 Louvain-la-Neuve, Belgium *Corresponding author: phone/fax +380445256177, e-mail: houk@lab15.kiev.ua Abstract. An accumulation mode SOI pMOSFET model for simulation of analog circuits meant for high-temperature applications is presented in the paper. The model is based on explicit expressions for the drain current with an infinite order of continuity what assures smooth transitions between different operation regimes of the transistor. This model is valid for all regimes of normal operation, demonstrates proper description of high-temperature behavior of the subthreshold and off-state current. The model characteristics show a good agreement with the experimental data for temperatures up to 300 °C. Keywords: high-temperature electronics, AM SOI pMOSFET, ∞C -continuous model. Manuscript received 10.10.05; accepted for publication 15.12.05. 1. Introduction Nowadays high-temperature electronics is a very important technology, especially for oil & gas, aerospace and automotive industries. Micronic silicon-on-insulator (SOI) CMOS technologies have proved to be the most mature for the 200-350 °C range of operation [1]. In particular, accumulation-mode (AM) SOI pMOSFETs appear very promising for the design of analog circuits operating in the wide temperature range (up to 350 °C)[1]. For developing these circuits, it is necessary to have an AM SOI pMOSFET model that is continuous in all regimes of operation, and derivatives of which are also continuous ( ∞C -continuous model). Such model has not been developed yet for high temperatures. In this paper, we present an extension to high temperatures of the room- temperature models developed by B. Iñiguez et al. [2, 3]. 2. Model As it is well known, the AM SOI MOSFETs feature three possible conduction modes: conduction through front and back accumulation layers (accumulation channels) and that through the non-depleted portion of the Si film, i.e., the quasi-neutral region (body channel) [4, 5]. The AM SOI pMOSFET model [2] accounts only two of these conduction modes, which are important under typical circuit operation (see Fig. 1b): body current and accumulation current, which appears when a portion of the front surface is in accumulation. I.e., the model is valid under the conditions, first, that the back surface of the Si film is always depleted, there are no mobile charge at the back interface and therefore current does not flow at the back interface; and second, the body current always appears in a central quasi-neutral region of the film before front accumulation develops (i.e., when the gate voltage is swept to negative values in a pMOSFET). However, there also exists a special case of full depletion of the AM SOI pMOSFET film by back-gate bias and positive charge in the buried oxide (BOX), which appears if the doping of Si film is low. This special case can be handled using the equations similar to the fully depleted (FD) SOI nMOSFET model [3]. This is justified because in both cases the Si film is fully-depleted, and the conduction takes place in the (accumulation or inversion) channel at the front Si/SiO2 interface [6]. Semiconductor Physics, Quantum Electronics & Optoelectronics, 2006. V. 9, N 1. P. 43-54. © 2006, V. Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine 44 Fig. 1. Cross section of an AM SOI pMOSFET (a) and conduction in an AM SOI pMOSFET with the front surface partially depleted, partially accumulated (b). Therefore, for the first time we develop a high- temperature model for AM SOI pMOSFETs based on the room-temperature models for AM SOI pMOSFETs [2] and FD enhancement mode (EM) nMOSFETs [3]. 2.1. Overview of room-temperature AM SOI pMOSFET model with body channel A. Front surface depleted The width of the body current path depends on the depth of the depletion regions controlled by the front and the back gates. The back depletion depth, dbx , can be assumed to be constant along the channel [4, 7] and equal to a fbbgb obob db qN VV cc x − +⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ +−= Si 2 SiSi 2ε εε . (1) The front depletion depth at a certain point of the channel can be written as a cfbfgf ofof df qN VVV cc x −− +⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ +−= Si 2 SiSi 2ε εε . (2) In (1) and (2), ofc and obc are the front and back oxide capacitances, Siε and aN are dielectric permittivity and doping level, respectively, gfV and gbV are the front and back gate voltages, respectively, and cV is the channel voltage in a given point of the channel. fbfV and fbbV are the front and back flat-band voltages. We define the effective film thickness as dbbb xtt −=eff, , where bt is the silicon film thickness. Therefore, the body channel thickness at each channel point is dfb xtx −= eff,ch . The mobile charge density in the body channel is obtained as chxqNq abc = . The threshold voltage fVth is defined at the minimum front gate voltage that pinches off the channel at 0=cV , that is [7] Si 2 eff,eff, th 2ε ab of ab fbff qNt c qNt VV ++= . However, even when the whole silicon film is fully depleted below the threshold, there is still a diffusion current component (the subthreshold component) that depends exponentially on fgf VV th− [8]. To develop a unified model, we have to consider both the drift (that dominates above the threshold) and the diffusion term (that dominates below threshold) of the body current. We define the effective potential ψ in order to extend (2) below the threshold, so that the resulting bcq is written as ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎣ ⎡ +⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ − −= 2 Si2 bt a gft btabc t qN V tqNq ε ψ , (3) where ofbbt ctt Sieff, ε+= , and fgfgft VVV th−= . Hence, (3) is a generalization of (2) in which we have replaced cV by the effective potential ψ in order to extend the validity of the expression of bcq into the subthreshold regime. In the subthreshold regime, bcq depends exponentially on fgf VV th− [8]. So, ψ tends to cV above the threshold, and in the subthreshold it tends to a value that gives such dependence of bcq . Therefore, the relationship between ψ and bcq is bcbt a bc dqt qN q d ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ −−= Si 1 ε ψ . (4) We write the body channel current as the sum of the drift and diffusion terms Semiconductor Physics, Quantum Electronics & Optoelectronics, 2006. V. 9, N 1. P. 43-54. © 2006, V. Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine 45 ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ −−= dx dq v dx d qWI bc Tbcbbcd ψ μ , (5) where bμ is the mobility in the silicon film, and qkTvT = is the thermal voltage. Using (3) in (4), we obtain the following expression of the body channel current when the front surface is fully depleted: ( ) ( ) ( ) , 2 3 1 ,, 2 , 2 , Si 3 , 3 , Si ⎥ ⎦ ⎤ −−−− ⎢ ⎣ ⎡ −−= sbcdbcTsbcdbc bt sbcdbc a bbcd qqvqq t qq qNL W I ε ε μ (6) where sbcq , and dbcq , are the body channel mobile charge densities at the source and drain ends, respectively. B. Front surface accumulated When a portion of the front surface is in accumulation, the accumulation charge density at a point of the surface can be written as [7] ( )cfbfgfofac VVVcq −−−= . (7) Writing the accumulation current as ( ) dxdVqWI cacacac −= μ ( acμ being the surface mo- bility) and using from (7) ofacc cdqdV = we get assuming the front surface is accumulated from source to drain ( ) ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎣ ⎡ −= 2 , 2 ,2 1 dacsac of acac qq cL WI μ , (8) where dacq , and sacq , are the accumulation charge densities at the source and drain ends, respectively, obtained from (7). When the front surface is fully accumulated, neglecting the thickness of the accumulation layer, the body current is written as ( ) ,,, eff, eff, sacdac of ba b dsbabbcnd qq c qtN L W VtqN L WI −= =−= μ μ (9) where ‘bcnd’ index stands for ‘Body Current at Non- Depleted front surface’, and dsV is the drain-source voltage. C. Front surface partly accumulated, partly depleted To develop a unified model, we have to assume that there can be a portion of the channel with accumulation at the surface (from the source, 0=x , to a length 1Lx = , see Fig. 1b) and a portion with depletion at the surface (from 1Lx = to the drain, Lx = ). By integrating the drift-diffusion equation from source to drain, we obtain ∫ ∫∫ −+ +−−= L L bcbcTb L Cbabacac L ds dqdqW dVtqNqWdxI 1 1 .)( )( 0 eff, 0 ψνμ μμ (10) To integrate, we make the following variable changes: between 0=x and 1Lx = we can write ofacc cdqdV = from (7). Between 1Lx = and Lx = , we can write bcbta dqtqNd ))(/1 Si −−= εψ from (4). To obtain an analytical solution, we assume that the effective mobilities bμ and acμ are independent of the position on the channel (as we will discuss below, acμ depends on the applied voltages). We get ( ) ( ) ( ) ( ) ( )⎥ ⎦ ⎤ −−−− ⎢ ⎣ ⎡ −−+ +−+ + ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎣ ⎡ −= pbcdbcTpbcdbc bt pbcdbc a b sacpac of ba b pacsac of acd qqvqqt qq qNL W qq c qtN L W qq cL WI ,, 2 , 2 , Si 3 , 3 , Si ,, eff, 2 , 2 , 2 3 1 2 1 ε ε μ μ μ (11) where pbcq , and pacq , are the quasi-neutral and accumulation charge densities at 1Lx = , respectively. Therefore, 0, =pacq and ff,, ebapbc tqNq = . Eq. (11) can be extended to all the possible regimes (including the surface accumulated from the source to drain and that depleted from the source to drain) replacing pacq , by dacq , and pbcq , by sbcq , : ( ) ( ) ( ) ( ) ( ) . 2 3 1 2 1 ,, 2 , 2 , Si 3 , 3 , Si ,, eff, 2 , 2 , ⎥ ⎦ ⎤ −−− ⎢ ⎣ ⎡ −−+ +−+ + ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎣ ⎡ −= sbcdbcTsbcdbc bt sbcdbc a b sacdac of ba b dacsac of acd qqvqq t qq qNL W qq c qtN L W qq cL W I ε ε μ μ μ (11') Semiconductor Physics, Quantum Electronics & Optoelectronics, 2006. V. 9, N 1. P. 43-54. © 2006, V. Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine 46 When the front surface is accumulated from the source to 1Lx = , 0, =dacq and eff,, basbc tqNq = , and therefore, (11') gives (11). When the front surface is accumulated from surface to drain, eff,,, badbcsbc tqNqq == , and (11') reduces to bcndacds III += as it should. When the front surface is depleted from the source to drain 0,, == dacsac qq , and (11') reduces to bcdds II = as it should, too. Therefore, we can write bcdbcndacds IIII ++= provided acI , bcndI and bcdI are written as (6), (8) and (9), respectively. Please, note that this does not mean that the total channel current is considered as the sum of three components in parallel; in fact these two components of the body current appear in series, but they are not written as (6) nor (9), because one component flows in a length equal to 1L and the other one flows in that equal to 1LL − . D. Continuous expressions To further develop the unified single-piece model, we need to approximate unified expressions for accumu- lation and quasi-neutral (body) charges at source and drain ends sacq , , dacq , , sbcq , , and dbcq , , respectively, valid from the subthreshold to total accumulation regime. We introduced the effective potential ψ in (3) for that. As an explicit expression, we use a suitable interpolation function gfteV instead of ψ−= gftgfti VV . Above the threshold, when cfbfgf VVV += , this interpolation function should smoothly give eff,babc tqNq = . So, we have the following expression for the quasi-neutral mobile charge density: 2 Si2gfte bc a bt bt a V q qN t t qN ε ⎡ ⎤⎛ ⎞ ⎢ ⎥= − +⎜ ⎟ ⎢ ⎥⎝ ⎠⎣ ⎦ (12) and ( )[ ]( ) [ ]( ) ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎣ ⎡ + −+ −= PS pegftePS pegfte A VVA VV exp1log 1exp1log 1 0 , (13) where ffbfpe VVV th−= , PSA in (3) is a fitting parameter that controls the transition from depletion to diffusion of the depleted charge in an AM SOI pMOSFET, it makes 1)exp( >>PSA , and 0gfteV is the following interpolation function: ( ) 2 00 2 0 4 gfteTTgfte VnvnvV +−= , (14) where ( ) ( ) . 2 exp 2 exp 1log 2 0 00 ⎟ ⎟ ⎠ ⎞ ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎣ ⎡ −− + ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎣ ⎡ −− + ⎜ ⎜ ⎜ ⎝ ⎛ +−= NTT cgft T cgft NTT NTTgfte Snv VV nv VV Snv v SnvV (15) NTS ( 1< ) is the parameter that controls the transition from below to above threshold, 0v is a fitting parameter that controls the magnitude of the body charge density above the threshold, and n corresponds to the subthreshold slope. Above the threshold and below the flat band ( cfgfcfbf VVVVV +<<+ th ), pegfte VV >0 and cgftgftegfte VVVV −≅≅ 0 , as it should; below threshold, still pegfte VV > and 0gftegfte VV ≅ , but from (14) and (15) we get that to the first order 0gfteV is proportional to ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ − − T cgft nv VV exp ; substituting (14) in (13) we obtain from (12) that bcq is, to the first order, proportional to ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ − − T cgft nv VV exp , as it should. Above the flat band pegfte VV <0 (note that for SOI pMOSFET 0gfteV and peV are both negative) and hence pegfte VV ≅ and eff,babc tqNq ≅ , as it should. In the expression for bcdI (6), we calculate sbcq , and dbcq , from Eqs (12)-(15) for cV equal to the source voltage sV and to the drain voltage dV , respectively, therefore bcdI tends smoothly to the desired limits in the different regimes. The diffusion term – the latter term in Eq. (6) – only dominates in the subthreshold regime. Due to intrinsic overestimation in the calculation of bcq by using Eq. (12), which can affect the near-threshold regime, we modify (6) by using, instead of Tv , the factor )(1 00 0 Td,gfteTs,gfte T T vVvV v v +− = , where sgfteV ,0 and dgfteV ,0 are calculated from Eq. (14) at sc VV = and dc VV = , respectively. Therefore, TT vv ≅0 in the subthreshold, as it should, and it tends to zero above the threshold. This modification improves the accuracy near the threshold. For the accumulation charge density, we present a useful unified expression that does not require interpolation functions more than those used to calculate sbcq , and dbcq , Semiconductor Physics, Quantum Electronics & Optoelectronics, 2006. V. 9, N 1. P. 43-54. © 2006, V. Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine 47 ( )gftegfteofac VVcq −−= 0 . (16) It is clear that (16) tends to the desired limits in all regimes. Below the flat band 0gftegfte VV ≅ and 0=acq . Above the flat band pegfte VV = and cfgftgfte VVVV −−= th0 and, hence, ( )cfbfgfofac VVVcq −−−= , as it should. Calculating sacq , and dacq , from (16) with sc VV = and dc VV = , we get an explicit ∞C -continuous model for acI and bcndI . Therefore, bcdbcndacds IIII ++= is the expression of the total channel current in all regimes. 2.2. Second-order effects Here we improve the model by including the second- order effects such as vertical and lateral field effects, channel-length modulation and series resistance [2]. Generally, influence of such effects is not very important at the used channel length, but it could be noticeable at large drain voltages (in the saturation regime), and become much more significant with decreasing the channel length. In this subsection, we describe briefly the main second-order corrections used in the model [2]. A. Vertical field effect In the above analysis, we have not considered the degradation of the surface mobility along the channel. However, we can keep the same equations using an effective surface mobility eff,acμ which accounts for mobility degradation with the average normal field in the accumulation channel. A useful expression for mobility degradation is sf ac ac Eα μ μ + = 1 eff, , (17) where ( ) Si,, 2εdacsacsf qqE += is the average field along the channel of the normal in the accumulation layer. There is no degradation of the body mobility bμ , since the normal field is low in the body region. B. Lateral field effect However, both the body and surface components of the current are affected by the velocity saturation effect. We assume that the drift velocity of charge carriers in the body can be written as ( ) [ ]( )dxdvdxdv bb ψμψμ sat21−= if bvdxd μψ sat2< and as satvv = if bvdxd μψ sat2> , where satv is the saturation velocity. Following the same procedure as in Section 2.1, but integrating the drift-diffusion equation from 0=x to effLx = ( effL being the effective length where the gradual channel approximation is valid, i.e., bvdxd μψ sat2< ; we will define this length later), we finally get the same expression of the body current bcndbcd II + as in the Section 2.1, but with bμ replaced by ( )bLdseb VV ,1−μ , where bbL LvV μeffsat, 2= , and dseV is the effective drain-source voltage. Assuming the same velocity-field relationship for the surface compo- nent, acI has the same expression as in Section 2.1, but with acμ replaced by ( )acLdseac VV ,eff, 1−μ , where eff,effsat, 2 acacL LvV μ= . dseV is defined as an interpolation function that tends to dsV in the linear regime and to saturation voltage satdV in the saturation one: ( )[ ]( ) [ ]( ) ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ + −+ −= TS ddsTS ddse A VVA VV exp1log 1exp1log 1 sat sat , (18) where TSA is a fitting parameter that controls the transition from the linear regime to saturation. In the subthreshold, the effect of saturation velocity is negligible and dseV should tend to zero. The saturation voltage is defined as the drain-source voltage, at which in the quasi-neutral region the carriers travel at a constant velocity, the saturation velocity satv . It is obtained by equating the expression of dsI to eff,sat bads tqNWvI = . In our case, it cannot be found analytically, so we use a special approximation again, valid in all operation regimes owing to the use of the interpolation function (14) bt VVds Tsgfte sgfte sgfted tWv I vV V VV sgftedse Sisat,0 ,0 ,0sat ,0 ε = − −= , (19) where sgftedse VVdsI ,0= is the unified expression of the drain current at sgftedse VV ,0= (that is, when dbcq , and dacq , are negligible). satdV tends to sgfteV ,0 in the subthreshold, which allows to get the desired expression of dbcq , , and above the threshold it tends to the desired saturation voltage. C. Channel length modulation When the body conduction is in the saturation regime, the channel length modulation effect has to be accounted for. We write sateff lLL −= , where satl is the modulated channel length: Semiconductor Physics, Quantum Electronics & Optoelectronics, 2006. V. 9, N 1. P. 43-54. © 2006, V. Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine 48 ⎟⎟ ⎟ ⎠ ⎞ ⎜⎜ ⎜ ⎝ ⎛ ++ = 2 2 2 2 11 sat log c ccc ll d , (20) where dseds VVc −=1 , bd vlc μsat2 = , and dl is the characteristic length that is considered as adjustable parameter. D. Series resistance The effect of the series drain and source resistance is included to the first order by a multiplication factor: idRd IfI ,= , (21) where idI , is the drain current expression without accounting for the series resistance and ( )2111 RRR aaf ++= , where , , 1 ,eff tot 2 ac s ac d R ac of of q qWa c R L c μ ⎛ ⎞+ = ⎜ ⎟⎜ ⎟ ⎝ ⎠ , (22) ( )dbcsbcbR qq L WR a ,, tot 2 2 += μ , (23) and totR is the total parasitic drain-source resistance. 2.3. Fully-depleted AM SOI pMOSFET room- temperature model Here we consider the case of fully-depleted low-doped AM SOI pMOSFET, deriving it from the FD EM SOI nMOSFET model [3]. A. Overview of FD EM SOI nMOSFET room- temperature model The ∞C -continuous FD enhancement mode (EM) SOI nMOSFET model [3] is based on the physical expression for the mobile charge density in the front inversion channel nfQ : ( ) ⎥ ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎢ ⎣ ⎡ +−= 2 2 24 11 TSof nf TSofnf vnc Q vncQ , (24) where Sn is the subthreshold slope ideality factor, and 2nfQ is a special approximation function: . 2 exp 2 exp 4 11log th ,th 2 ⎥ ⎥ ⎦ ⎤ ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ −− + ⎢ ⎢ ⎣ ⎡ +⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ −− +× ×−= NTTS cfgf TS cSifGf NT NTTSofnf Svn nVVV vn VnVV S SvncQ (25) In (25) the second term in the logarithm dominates in weak inversion and the third one in strong inversion. Here n stands for the body factor in strong inversion. NTS controls the transition from weak to strong inversion ( 1<NTS ). ifV ,th being the front threshold voltage which corresponds to a surface potential of cV+F2φ ( Fφ is the Fermi potential). While this threshold value appears in a weak inversion term of (25), a different value is introduced in the strong inversion term, fVth , to take into account that the strong inversion surface potential is always larger than cV+F2φ by a few Tv . This capability to use two threshold voltages is an advantage over other models, which have to artificially overestimate the mobility degradation, especially for moderate gfV , in order to account for the threshold voltage increase from weak to strong inversion [9]. These two threshold voltages could be expressed as gbifif VnVV )1(,0th,th −−= and gbff VnVV )1(0thth −−= , where ifV ,0th and 0th fV could be considered as fitting parameters or derived from other technology parameters. The interpolation function (24) tends to the desired physically proper limits in weak and strong inversion and yields continuous expression for the current: ( ) ⎥ ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎢ ⎣ ⎡ − −−= of snfdnf snfdnfTnd nc QQ QQv L W I 2 2 , 2 , ,,μ , (26) where nμ is the electron mobility, snfQ , and dnfQ , are the inversion charge densities at the source and drain edges, calculated from (26) for cV equal to source voltage sV and to drain voltage dV , respectively. B. Customization for the case of FD low-doped AM SOI pMOSFET Therefore an explicit ∞C -continuous model for FD EM nMOSFET is obtained in previous subsection. Here we demonstrate that it can be customized for the case of FD low-doped AM pMOSFET by appropriate change of voltage signs. Other device type dependent parameters, such as surface potentials, zero for weak accumulation and a few Tv lower for strong accumulation, are fully encapsulated in the two threshold voltages ifV ,0th and 0th fV , which could be considered as fitting parameters again, or calculated from technological parameters of AM pMOSFET devices following [10]: th 0, 2 2 a b bb a b f i fbf fbb of of ob qN t c qN tV V V c c c ⎛ ⎞ = + − − −⎜ ⎟ ⎝ ⎠ , (27a) th 0 th 0,f f i S saV V n φ= + . (27b) Semiconductor Physics, Quantum Electronics & Optoelectronics, 2006. V. 9, N 1. P. 43-54. © 2006, V. Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine 49 Here bbc is the capacitance of the film and the back oxide in series, ( )obbobbbb ccccc += , where bb tc Siε= is the film capacitance, and saφ is the surface potential of strong accumulation. Now we can use ifV ,th and fVth in (25) with appropriate change of signs. The second-order effects are introduced similarly as described in Section 2.2, for details please refer the original paper [3]. 2.4. Developing of high-temperature model A. General temperature dependences Due to the fact that the ∞C -continuous model described above was developed on physical principles and depends only on physical parameters of the device, there is clear possibility to introduce temperature dependences of all the parameters. Temperature dependences of all the main parameters of AM SOI pMOSFET (intrinsic carrier concentration in , bandgap width gE , mobility μ , etc.) are well-known [11]. However, this is not enough to develop the high-temperature model, because some assumptions of the described above model are not valid at high temperatures. B. Subthreshold slope at high temperatures The main problem is that the potential distribution in the film at high temperatures differs significantly from the potential distribution at room temperature, and the charge-sheet model approximation which is used in the ∞C -continuous models [2, 3] described in the previous sections becomes inaccurate [12]. As a result, we have considerable disagreement between the model and experimental curves in the subthreshold and off-state regions, while off-state currents at high temperatures becomes extremely large and can influence the normal operation of devices, so proper modeling of them is necessary. The models like [2, 3] described above predict linear behavior of the subthreshold slope dependence upon temperature, while our experiment states that this dependence is highly nonlinear. This was explained using numerical simulation by prevalence of diffusion component of current [12]. Instead of numerical simulations, we used an empirical dependence extracted from experimental data: a combination of 3rd power polynomial and exponential dependences (see Fig. 2): 43 3 2 300 1 e CTCTCCS T +++= − , (28) with the coefficients 1 1 V41.2 −=C , 318 2 KV1007.4 −−−⋅−=C , 11 3 KV01.0 −−−=C and 1 4 V23.2 −−=C . C. High-temperature off-state currents We consider two components of the off-state leakage currents in the accumulation mode p-channel device: current due to the thermal generation in the body film bulk (diffusion current) and current due to the thermal generation in the drain-depleted body film region (generation current). The diffusion component is expressed as [11] ( ) c b a ivV Tbosd L Wt N qn vI TD 2 e1−= μ , (29) where cL is the diffusion length (or the effective device length if the latter is shorter). As it was showed previously [12], the total carrier density responsible for the diffusion component in the case of accumulation mode p-channel devices is the same as in the case of the enhancement mode n-channel ones, so we used common approximation for minority carrier density a i N qn2 . The generation current in the depleted region of the body near the drain is expressed as [11] bi g i osg tWL qn I τ = , (30) where ⎪⎭ ⎪ ⎬ ⎫ ⎪⎩ ⎪ ⎨ ⎧ ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ −−⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ = i a T D i a a T i n N v qV n N N v L lnln 2 Siε , (31) iL stands for the depth of depleted region near the drain, where the thermal generation rate is maximal and outside of it the rate is negligible, gτ is the generation lifetime. Therefore, the total off-state current is osgosd III +=off . (32) 3 0 0 3 5 0 4 0 0 4 5 0 5 0 0 5 5 0 6 0 0 0 . 0 5 0 . 1 0 0 . 1 5 0 . 2 0 0 . 2 5 0 . 3 0 0 . 3 5 Drain voltage -0.1V Backgate voltage 0V Su bt hr es ho ld s w in g (d ec V -1 ) Temperature (K) symbols - experiment line - empirical model: S = 2.41exp(T/300)-4.07x10-8T3 - 0.01T-2.23 Fig. 2. Empirical dependence of the subthreshold slope upon temperature derived from experimental data. Semiconductor Physics, Quantum Electronics & Optoelectronics, 2006. V. 9, N 1. P. 43-54. © 2006, V. Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine 50 - 3 . 5 - 3 . 0 - 2 . 5 - 2 . 0 - 1 . 5 - 1 . 0 - 0 . 5 0 . 0 0 . 5 0 . 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 -0.05V -2V Drain voltage 0V -1.5V Backgate voltage +1.5V D ra in c ur re nt ( mA) Front-gate voltage (V) (a) symbols - experiment lines - model - 3 . 5 - 3 . 0 - 2 . 5 - 2 . 0 - 1 . 5 - 1 . 0 - 0 . 5 0 . 0 0 . 5 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 -0.05V -2V Drain voltage 0V -1.5V Backgate voltage +1.5V D ra in c ur re nt ( mA) Front-gate voltage (V) (b) symbols - experiment lines - model Fig. 3. Results of modeling the transfer characteristics ( gdVI ) at room temperature for various back-gate biases in the linear (a) and saturation (b) regimes. 3. Results and discussion 3.1. Fully-depleted AM SOI pMOSFET room- temperature model The obtained model was validated using experimental data, obtained for AM SOI pMOSFET devices, fabricated on UNIBOND material in DICE, UCL (Belgium). The devices possessed the following parameters: the front gate oxide, film and BOX thicknesses were 308, 889 and 4000 Å, the channel doping was 316 cm162 −× only, and the channel length and width were L = W = 20 μm. Temperature measurements were performed up to 300 °C. Due to low doping of the Si film, we have the case of fully-depleted AM SOI pMOSFET. Using the model, it is possible to find values of device parameters by fitting the model curve to experimental data. For this aim, the method of Fast Simulated Diffusion was used [13], especially developed for resolving of multidimensional minimization problems like MOSFET modeling is. The found values of main parameters at room temperature are shown in Table. The model also accounts the effect of decreasing the device length and width during technological processes of device manufacturing, i.e., doping of the source and drain region and forming the side oxides. The appropriate corrections, lateral diffusion length for the channel length, and diffusion width for the width were determined and listed in Table. In Fig. 3, we demonstrate the comparison of the experimental and model curves of the transistor transfer characteristics ( gdVI ) at room temperature both in linear (drain voltage V05.0−=dsV , see Fig. 3a) and saturation ( V2−=dsV , see Fig. 3b) regimes of operation for different back-gate bias voltages. In Fig. 4, we compare the same curves in the logarithmic scale to see the results of modeling in the subthreshold region. It is clearly seen that the model shows a good agreement with measurements in all the regions from subthreshold (Fig. 4) to above threshold voltages (Fig. 3) both in linear and saturation regimes. Table. Determined values of MOSFET parameters and their temperature dependences. Parameter Room-temp. value Temperature dependence(11) (parameters refitted) Weak accumulation threshold voltage, r i V ,0th , V −0.38 ( )room 3 ,0th,0th 10 TTVV r ii −+= − Strong accumulation threshold voltage, rV 0th , V −0.41 the same Hole mobility, m2/(V⋅s) - in accum. channel, 0acμ 0.0211 ( ) 6.1 room0 −= TTμμ - in body channel, 0bμ 0.0291 Field mobility degr. factor, 0fα , m/V 81065.1 −× ( ) 05.2 room0 −= TTff αα Lateral diffusion length, latl , m 71068.8 −× Diffusion width, dw , m 61016.1 −× Source/drain series resist., totR , Ohm 220 Saturation rate, 0satv , m/s 4100.8 × ( ) ( )room 0satsat 2/exp8.01 2/1exp8.01 TT vv + + = Characteristic length, dl , m 81009.2 −× Generation lifetime, 0gτ , s 7109.0 −× ( )TTg 64.213 1013.1cosh10 −− ×=τ Recombination lifetime, 0rτ , s 6101.0 −× ( ) 7.2 room0 TTrr ττ = Semiconductor Physics, Quantum Electronics & Optoelectronics, 2006. V. 9, N 1. P. 43-54. © 2006, V. Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine 51 - 3 . 5 - 3 . 0 - 2 . 5 - 2 . 0 - 1 . 5 - 1 . 0 - 0 . 5 0 . 0 0 1 2 3 4 5 200°C 300°C 100°C -0.1V -2V Drain voltage 30°C Backgate voltage 0V D ra in c ur re nt ( mA) Front-gate voltage (V) (a) symbols - experiment lines - model temperature - 3 . 5 - 3 . 0 - 2 . 5 - 2 . 0 - 1 . 5 - 1 . 0 - 0 . 5 0 . 0 0 1 0 2 0 3 0 4 0 5 0 6 0 200°C 300°C 100°C -0.1V -2V Drain voltage 30°C Backgate voltage 0V D ra in c ur re nt ( mA) Front-gate voltage (V) (b) symbols - experiment lines - model temperature Fig. 6. Transfer characteristics ( gdVI ) at high temperatures for zero back-gate bias in the linear (a) and saturation (b) regimes. - 3 - 2 - 1 0 1 2 1 0 - 1 2 1 0 - 1 1 1 0 - 1 0 1 0 - 9 1 0 - 8 1 0 - 7 1 0 - 6 1 0 - 5 -0.05V -2V Drain voltage D ra in c ur re nt (A ) Front-gate voltage (V) symbols - experiment lines - model 0V -1.5V Backgate voltage: +1.5V Fig. 4. Transfer characteristics ( gdVI ) at room temperature for various back-gate biases in the subthreshold region. In Fig. 5, we compare the model and measured output characteristics ( ddVI ) at room temperatures. One can observe a good agreement for all the regimes of operation, from the linear to saturation ones. 3.2. High-temperature simulations With regards to the main result of this work, i.e., modeling the high-temperature AM MOSFET characteristics, the temperature dependences of the main model parameters are presented in Table. Fig. 6 shows a comparison of the measured and model gdVI curves for AM SOI pMOSFET at high temperatures. As one can see, modeled characteristics show a good agreement with experimental results in the wide range of temperatures (from the room temperature up to 300 °C) in linear (Fig. 6a) and saturation (Fig. 6b) regimes. A very important feature for analog design, i.e. the zero-temperature coefficient (ZTC) point, corresponding to a constant gdVI bias point with temperature, is particularly well modeled, too. - 3 . 0 - 2 . 5 - 2 . 0 - 1 . 5 - 1 . 0 - 0 . 5 0 . 0 0 2 4 6 8 1 0 1 2 -0.6V -0.3V Frontgate voltage -1.2V -1.5V Backgate voltage 0V -0.9VD ra in c ur re nt ( mA) Drain voltage (V) symbols - experiment lines - model Fig. 5. The output characteristics ( ddVI ) at room temperature for zero back-gate bias. The same characteristics, depicted in the logarithmic scale in Fig. 7a, show the behavior of the model curves in the subthreshold and off-state regions. As one can see, the subthreshold swing dependence upon temperature is very good. The model curves exhibit smooth transition between all the regimes of operation (from the off-state through subthreshold to the above threshold region). Also, the off-state current temperature dependence is correctly modeled. In Fig. 7b, we have more vivid picture of this dependence. The model curves demon- strate proper quantitative and qualitative description of the off-state current dependence upon temperature. As it should be expected, we have significant difference between the saturation and linear off-state currents at low temperatures, which is explained by increasing the generation current (30) at high absolute values of the drain voltage, because of increasing the depth of the depleted region near the drain [see Eq. (31)], where generation takes place. At the same time, the diffusion component of the off-state current (29) tends to saturate with the drain voltage. Concerning the temperature dependence of both components of leakage current, the generation component (30) increases with temperature as )(Tni , while the diffusion one (29) varies as )(2 Tni . At Semiconductor Physics, Quantum Electronics & Optoelectronics, 2006. V. 9, N 1. P. 43-54. © 2006, V. Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine 52 - 3 - 2 - 1 0 1 2 1 0 - 1 3 1 0 - 1 2 1 0 - 1 1 1 0 - 1 0 1 0 - 9 1 0 - 8 1 0 - 7 1 0 - 6 1 0 - 5 200°C 300°C 100°C -0.1V -2V Drain voltage 30°C Backgate voltage 0V D ra in c ur re nt (A ) Front-gate voltage (V) (a) symbols - experiment thick lines - linear model thin lines - saturation model temperature 3 0 0 3 5 0 4 0 0 4 5 0 5 0 0 5 5 0 6 0 0 1 0 - 1 4 1 0 - 1 3 1 0 - 1 2 1 0 - 1 1 1 0 - 1 0 1 0 - 9 1 0 - 8 Frontgate voltage 1.5V -0.1V -2V Drain voltage Backgate voltage 0V O ff- st at e dr ai n cu rre nt (A ) Temperature (K) (b) symbols - experiment lines - model Fig. 7. Transfer characteristics ( gdVI ) at high temperatures for zero back-gate bias in the subthreshold region (a) and the off- state current vs temperature (b). 3 0 0 3 5 0 4 0 0 4 5 0 5 0 0 5 5 0 6 0 0 - 0 . 5 - 0 . 4 - 0 . 3 - 0 . 2 - 0 . 1 0 . 0 Drain voltage -0.1V Backgate voltage 0V Th re sh ol d vo lta ge (V ) Temperature (K) (a) symbols - experiment line - model - 3 - 2 - 1 0 1 2 0 1 2 3 4 5 - 4 0 4 8 x 1 0 - 6 (b) Threshold position 2nd derivative Drain voltage -0.1V Backgate voltage 0V D ra in c ur re nt ( mA) Front-gate voltage (V) Experimental Id-Vg Room temperature d 2 I d/d V2 g ( AV 2 ) Fig. 8. Comparison of the experimental and model dependences for the threshold voltage upon temperature for zero back-gate bias (a) and an illustration of the 2nd derivative method for determining the threshold voltage (b). high temperatures the diffusion current increases significantly, and it becomes the dominant component of the leakage current. Therefore, the difference between off-state currents in the saturation and linear regimes caused by the generation component becomes slighter at high temperatures, as clearly seen from Fig. 7b. The same feature of leakage current behavior at high temperatures was reported previously [12]. In Fig. 8a, comparing the experimental and model threshold voltage dependences upon temperature is presented. The experimental values of the threshold voltage were obtained from the experimental gdVI curves by using the 2nd derivative method [14] (simple illustration of the method is depicted in Fig. 8b). Model curves are straight lines according to the chosen dependence of the threshold voltage upon temperature, and taking the dispersion of experimental values into consideration, model curves show a good coincidence with the experimental ones (Fig. 8a). The important analog parameter dm Ig ( mg being the transconductance gfdm dVdIg = ) for different temperatures is plotted in Fig. 9. When the value of dm Ig is the largest ones, the maximum voltage gain of a MOSFET is obtained [7]. As Fig. 9a shows, the maximum of this parameter is getting lower with increase of temperature, due to the degradation of subthreshold operation, which infers that the maximum voltage gain of the device is significantly decreased. Nevertheless, when biasing the devices at the ZTC point, to maintain constant bias with temperature for analog circuits such as amplifiers [15], we observe and correctly model a much reduced degradation of the dm Ig coefficient with temperature (Fig. 9b). The gate-source intrinsic capacitance ( sggs dVdQC −= ) measurements at the temperature 300 °C compared to the model curves are plotted in Fig. 10. Experimental data were taken from the data for the transistor with the front gate oxide, film and BOX thicknesses of 550, 1000 and 4200 Å, the channel doping of 316 cm108 −× , and with the channel length and width of μm20 [4]. There is also a good agreement through all the regimes for different values of the drain voltage. Semiconductor Physics, Quantum Electronics & Optoelectronics, 2006. V. 9, N 1. P. 43-54. © 2006, V. Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine 53 1 0 - 1 5 1 0 - 1 3 1 0 - 1 1 1 0 - 9 1 0 - 7 1 0 - 5 - 1 0 0 1 0 2 0 3 0 4 0 (a) 200°C 300°C 100°C Drain voltage -0.1V 30°C Backgate voltage 0V g m /I d ( 1/ V) Drain current Id (A) symbols - experiment lines - model temperature 3 0 0 3 5 0 4 0 0 4 5 0 5 0 0 5 5 0 6 0 0 2 3 4 5 6 7 Section at ZTC point (current level 3.4x10-7A) Frontgate voltage -0.6V (b) -0.1V Drain voltage Backgate voltage 0V g m /I ds (1 /V ) Temperature (K) symbols - experiment lines - model Fig. 9. Results of modeling the transconductance ( dm Ig vs dI ) at high temperatures (a) and a section of this dependence at ZTC point (b). - 4 - 2 0 0 . 0 0 0 . 0 2 0 . 0 4 0 . 0 6 0 . 0 8 0 . 1 0 0 . 1 2 0 . 1 4 0 . 1 6 0 . 1 8 Source voltage 0V -1V -0.05V -4V Drain voltage Backgate voltage 0V G at e- so ur ce c ap ac ita nc e (p F) Front-gate voltage (V) symbols - experiment lines - model Fig. 10. Gate-source intrinsic capacitance ( gsC vs gfV ) at the high temperature (300 °C). 4. Conclusions The high-temperature AM SOI p-MOSFET model has been developed in the paper. The model is based on the approximate ∞C -continuous expressions of the accumulation and quasi-neutral charge densities. The obtained agreement between the model and experimental data for AM SOI p-MOSFET characteristics is very good. We specifically developed new formulations for the subthreshold slope and off-state currents. The model works properly in all the operation regimes including subthreshold and off-state conduction in the range from the room temperature up to 300 °C. A smooth transition between different operation regimes, as well as proper modeling the AC and DC MOSFET characteristics (ZTC, transconductance-to-drain current ratio, intrinsic capacitances) is demonstrated, which allows to use the model for high-temperature analog circuits simulations. Acknowledgements The work was performed in the frame of SPRING project (project #IST-1999-12342), and also was partially supported by NATO CLG (PST CLG 979999). The authors are thankful to T.E. Rudenko, V. Kilchytska and A. Tuor for helpful discussions. References 1. D. Flandre, S. Adriaensen, A. Akheyar, A. Crahay, L. Demeus et al., Fully depleted SOI CMOS technology for heterogeneous micropower, high- temperature or RF Microsystems // Solid State Electron. 45(4) p. 541–549 (2001). 2. B. Iñiguez, B. Gentinne, V. Dessard, D. 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